fbc1feb39a
Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
237 lines
4.2 KiB
INI
237 lines
4.2 KiB
INI
[root]
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type=Root
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children=system
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full_system=false
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time_sync_enable=false
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time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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[system]
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type=System
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children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
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boot_osflags=a
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cache_line_size=64
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clk_domain=system.clk_domain
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init_param=0
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kernel=
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load_addr_mask=1099511627775
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mem_mode=timing
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mem_ranges=
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memories=system.physmem
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num_work_ids=16
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readfile=
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symbolfile=
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.slave[0]
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[system.clk_domain]
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type=SrcClockDomain
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clock=1000
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voltage_domain=system.voltage_domain
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[system.cpu]
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type=TimingSimpleCPU
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children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
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checker=Null
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clk_domain=system.cpu_clk_domain
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cpu_id=0
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do_checkpoint_insts=true
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do_quiesce=true
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do_statistics_insts=true
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dtb=system.cpu.dtb
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function_trace=false
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function_trace_start=0
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interrupts=system.cpu.interrupts
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isa=system.cpu.isa
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itb=system.cpu.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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profile=0
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progress_interval=0
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simpoint_start_insts=
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switched_out=false
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system=system
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tracer=system.cpu.tracer
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workload=system.cpu.workload
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dcache_port=system.cpu.dcache.cpu_side
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icache_port=system.cpu.icache.cpu_side
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[system.cpu.dcache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=2
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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size=262144
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system=system
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tags=system.cpu.dcache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.dcache_port
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mem_side=system.cpu.toL2Bus.slave[1]
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[system.cpu.dcache.tags]
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type=LRU
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assoc=2
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=2
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size=262144
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[system.cpu.dtb]
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type=SparcTLB
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size=64
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[system.cpu.icache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=2
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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size=131072
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system=system
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tags=system.cpu.icache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.icache_port
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mem_side=system.cpu.toL2Bus.slave[0]
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[system.cpu.icache.tags]
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type=LRU
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assoc=2
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=2
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size=131072
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[system.cpu.interrupts]
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type=SparcInterrupts
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[system.cpu.isa]
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type=SparcISA
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[system.cpu.itb]
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type=SparcTLB
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size=64
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[system.cpu.l2cache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=8
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=20
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is_top_level=false
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max_miss_count=0
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mshrs=20
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prefetch_on_access=false
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prefetcher=Null
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response_latency=20
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size=2097152
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system=system
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tags=system.cpu.l2cache.tags
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tgts_per_mshr=12
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.toL2Bus.master[0]
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mem_side=system.membus.slave[1]
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[system.cpu.l2cache.tags]
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type=LRU
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assoc=8
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=20
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size=2097152
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[system.cpu.toL2Bus]
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type=CoherentBus
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clk_domain=system.cpu_clk_domain
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header_cycles=1
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system=system
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use_default_range=false
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width=32
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master=system.cpu.l2cache.cpu_side
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slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
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[system.cpu.tracer]
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type=ExeTracer
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[system.cpu.workload]
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type=LiveProcess
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cmd=hello
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cwd=
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egid=100
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env=
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errout=cerr
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euid=100
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executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
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gid=100
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input=cin
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max_stack_size=67108864
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output=cout
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pid=100
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ppid=99
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simpoint=0
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system=system
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uid=100
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[system.cpu_clk_domain]
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type=SrcClockDomain
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clock=500
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voltage_domain=system.voltage_domain
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[system.membus]
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type=CoherentBus
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clk_domain=system.clk_domain
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header_cycles=1
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system=system
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use_default_range=false
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width=8
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master=system.physmem.port
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slave=system.system_port system.cpu.l2cache.mem_side
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[system.physmem]
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type=SimpleMemory
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bandwidth=73.000000
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clk_domain=system.clk_domain
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conf_table_reported=true
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in_addr_map=true
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latency=30000
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latency_var=0
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null=false
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range=0:134217727
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port=system.membus.master[0]
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[system.voltage_domain]
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type=VoltageDomain
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voltage=1.000000
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