fbc1feb39a
Apparently only stats.txt was updated the last time, so this changeset updates other reference output files (config.ini, simout, simerr, ruby.stats) so that test output diffs should not be cluttered with irrelevant changes. There are a few stats.txt updates too, but they are in the minority.
594 lines
11 KiB
INI
594 lines
11 KiB
INI
[root]
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type=Root
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children=system
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full_system=false
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time_sync_enable=false
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time_sync_period=100000000000
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time_sync_spin_threshold=100000000
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[system]
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type=System
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children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
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boot_osflags=a
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cache_line_size=64
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clk_domain=system.clk_domain
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init_param=0
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kernel=
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load_addr_mask=1099511627775
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mem_mode=timing
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mem_ranges=
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memories=system.physmem
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num_work_ids=16
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readfile=
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symbolfile=
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work_begin_ckpt_count=0
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work_begin_cpu_id_exit=-1
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work_begin_exit_count=0
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work_cpus_ckpt_count=0
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work_end_ckpt_count=0
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work_end_exit_count=0
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work_item_id=-1
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system_port=system.membus.slave[0]
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[system.clk_domain]
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type=SrcClockDomain
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clock=1000
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voltage_domain=system.voltage_domain
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[system.cpu]
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type=DerivO3CPU
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children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
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LFSTSize=1024
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LQEntries=32
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LSQCheckLoads=true
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LSQDepCheckShift=4
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SQEntries=32
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SSITSize=1024
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UnifiedTLB=true
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activity=0
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backComSize=5
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branchPred=system.cpu.branchPred
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cachePorts=200
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checker=Null
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clk_domain=system.cpu_clk_domain
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commitToDecodeDelay=1
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commitToFetchDelay=1
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commitToIEWDelay=1
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commitToRenameDelay=1
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commitWidth=8
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cpu_id=0
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decodeToFetchDelay=1
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decodeToRenameDelay=1
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decodeWidth=8
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dispatchWidth=8
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do_checkpoint_insts=true
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do_quiesce=true
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do_statistics_insts=true
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dtb=system.cpu.dtb
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fetchToDecodeDelay=1
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fetchTrapLatency=1
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fetchWidth=8
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forwardComSize=5
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fuPool=system.cpu.fuPool
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function_trace=false
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function_trace_start=0
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iewToCommitDelay=1
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iewToDecodeDelay=1
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iewToFetchDelay=1
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iewToRenameDelay=1
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interrupts=system.cpu.interrupts
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isa=system.cpu.isa
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issueToExecuteDelay=1
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issueWidth=8
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itb=system.cpu.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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needsTSO=false
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numIQEntries=64
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numPhysFloatRegs=256
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numPhysIntRegs=256
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numROBEntries=192
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numRobs=1
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numThreads=1
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profile=0
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progress_interval=0
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renameToDecodeDelay=1
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renameToFetchDelay=1
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renameToIEWDelay=2
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renameToROBDelay=1
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renameWidth=8
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simpoint_start_insts=
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smtCommitPolicy=RoundRobin
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smtFetchPolicy=SingleThread
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smtIQPolicy=Partitioned
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smtIQThreshold=100
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smtLSQPolicy=Partitioned
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smtLSQThreshold=100
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smtNumFetchingThreads=1
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smtROBPolicy=Partitioned
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smtROBThreshold=100
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squashWidth=8
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store_set_clear_period=250000
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switched_out=false
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system=system
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tracer=system.cpu.tracer
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trapLatency=13
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wbDepth=1
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wbWidth=8
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workload=system.cpu.workload
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dcache_port=system.cpu.dcache.cpu_side
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icache_port=system.cpu.icache.cpu_side
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[system.cpu.branchPred]
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type=BranchPredictor
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BTBEntries=4096
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BTBTagSize=16
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RASSize=16
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choiceCtrBits=2
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choicePredictorSize=8192
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globalCtrBits=2
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globalPredictorSize=8192
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instShiftAmt=2
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localCtrBits=2
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localHistoryTableSize=2048
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localPredictorSize=2048
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numThreads=1
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predType=tournament
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[system.cpu.dcache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=2
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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size=262144
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system=system
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tags=system.cpu.dcache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.dcache_port
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mem_side=system.cpu.toL2Bus.slave[1]
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[system.cpu.dcache.tags]
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type=LRU
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assoc=2
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=2
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size=262144
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[system.cpu.dtb]
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type=PowerTLB
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size=64
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[system.cpu.fuPool]
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type=FUPool
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children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
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FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
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[system.cpu.fuPool.FUList0]
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type=FUDesc
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children=opList
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count=6
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opList=system.cpu.fuPool.FUList0.opList
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[system.cpu.fuPool.FUList0.opList]
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type=OpDesc
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issueLat=1
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opClass=IntAlu
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opLat=1
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[system.cpu.fuPool.FUList1]
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type=FUDesc
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children=opList0 opList1
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count=2
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opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
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[system.cpu.fuPool.FUList1.opList0]
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type=OpDesc
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issueLat=1
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opClass=IntMult
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opLat=3
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[system.cpu.fuPool.FUList1.opList1]
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type=OpDesc
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issueLat=19
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opClass=IntDiv
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opLat=20
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[system.cpu.fuPool.FUList2]
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type=FUDesc
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children=opList0 opList1 opList2
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count=4
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opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
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[system.cpu.fuPool.FUList2.opList0]
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type=OpDesc
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issueLat=1
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opClass=FloatAdd
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opLat=2
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[system.cpu.fuPool.FUList2.opList1]
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type=OpDesc
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issueLat=1
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opClass=FloatCmp
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opLat=2
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[system.cpu.fuPool.FUList2.opList2]
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type=OpDesc
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issueLat=1
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opClass=FloatCvt
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opLat=2
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[system.cpu.fuPool.FUList3]
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type=FUDesc
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children=opList0 opList1 opList2
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count=2
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opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
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[system.cpu.fuPool.FUList3.opList0]
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type=OpDesc
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issueLat=1
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opClass=FloatMult
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opLat=4
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[system.cpu.fuPool.FUList3.opList1]
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type=OpDesc
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issueLat=12
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opClass=FloatDiv
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opLat=12
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[system.cpu.fuPool.FUList3.opList2]
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type=OpDesc
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issueLat=24
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opClass=FloatSqrt
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opLat=24
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[system.cpu.fuPool.FUList4]
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type=FUDesc
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children=opList
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count=0
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opList=system.cpu.fuPool.FUList4.opList
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[system.cpu.fuPool.FUList4.opList]
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type=OpDesc
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issueLat=1
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opClass=MemRead
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opLat=1
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[system.cpu.fuPool.FUList5]
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type=FUDesc
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children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
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count=4
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opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
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[system.cpu.fuPool.FUList5.opList00]
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type=OpDesc
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issueLat=1
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opClass=SimdAdd
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opLat=1
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[system.cpu.fuPool.FUList5.opList01]
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type=OpDesc
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issueLat=1
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opClass=SimdAddAcc
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opLat=1
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[system.cpu.fuPool.FUList5.opList02]
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type=OpDesc
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issueLat=1
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opClass=SimdAlu
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opLat=1
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[system.cpu.fuPool.FUList5.opList03]
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type=OpDesc
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issueLat=1
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opClass=SimdCmp
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opLat=1
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[system.cpu.fuPool.FUList5.opList04]
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type=OpDesc
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issueLat=1
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opClass=SimdCvt
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opLat=1
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[system.cpu.fuPool.FUList5.opList05]
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type=OpDesc
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issueLat=1
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opClass=SimdMisc
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opLat=1
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[system.cpu.fuPool.FUList5.opList06]
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type=OpDesc
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issueLat=1
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opClass=SimdMult
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opLat=1
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[system.cpu.fuPool.FUList5.opList07]
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type=OpDesc
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issueLat=1
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opClass=SimdMultAcc
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opLat=1
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[system.cpu.fuPool.FUList5.opList08]
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type=OpDesc
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issueLat=1
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opClass=SimdShift
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opLat=1
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[system.cpu.fuPool.FUList5.opList09]
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type=OpDesc
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issueLat=1
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opClass=SimdShiftAcc
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opLat=1
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[system.cpu.fuPool.FUList5.opList10]
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type=OpDesc
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issueLat=1
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opClass=SimdSqrt
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opLat=1
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[system.cpu.fuPool.FUList5.opList11]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatAdd
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opLat=1
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[system.cpu.fuPool.FUList5.opList12]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatAlu
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opLat=1
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[system.cpu.fuPool.FUList5.opList13]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatCmp
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opLat=1
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[system.cpu.fuPool.FUList5.opList14]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatCvt
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opLat=1
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[system.cpu.fuPool.FUList5.opList15]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatDiv
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opLat=1
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[system.cpu.fuPool.FUList5.opList16]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatMisc
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opLat=1
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[system.cpu.fuPool.FUList5.opList17]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatMult
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opLat=1
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[system.cpu.fuPool.FUList5.opList18]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatMultAcc
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opLat=1
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[system.cpu.fuPool.FUList5.opList19]
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type=OpDesc
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issueLat=1
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opClass=SimdFloatSqrt
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opLat=1
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[system.cpu.fuPool.FUList6]
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type=FUDesc
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children=opList
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count=0
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opList=system.cpu.fuPool.FUList6.opList
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[system.cpu.fuPool.FUList6.opList]
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type=OpDesc
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issueLat=1
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opClass=MemWrite
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opLat=1
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[system.cpu.fuPool.FUList7]
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type=FUDesc
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children=opList0 opList1
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count=4
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opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
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[system.cpu.fuPool.FUList7.opList0]
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type=OpDesc
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issueLat=1
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opClass=MemRead
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opLat=1
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[system.cpu.fuPool.FUList7.opList1]
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type=OpDesc
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issueLat=1
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opClass=MemWrite
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opLat=1
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[system.cpu.fuPool.FUList8]
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type=FUDesc
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children=opList
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count=1
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opList=system.cpu.fuPool.FUList8.opList
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[system.cpu.fuPool.FUList8.opList]
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type=OpDesc
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issueLat=3
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opClass=IprAccess
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opLat=3
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[system.cpu.icache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=2
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=2
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is_top_level=true
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max_miss_count=0
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mshrs=4
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prefetch_on_access=false
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prefetcher=Null
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response_latency=2
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size=131072
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system=system
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tags=system.cpu.icache.tags
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tgts_per_mshr=20
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.icache_port
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mem_side=system.cpu.toL2Bus.slave[0]
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[system.cpu.icache.tags]
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type=LRU
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assoc=2
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=2
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size=131072
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[system.cpu.interrupts]
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type=PowerInterrupts
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[system.cpu.isa]
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type=PowerISA
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[system.cpu.itb]
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type=PowerTLB
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size=64
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[system.cpu.l2cache]
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type=BaseCache
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children=tags
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addr_ranges=0:18446744073709551615
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assoc=8
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clk_domain=system.cpu_clk_domain
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forward_snoops=true
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hit_latency=20
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is_top_level=false
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max_miss_count=0
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mshrs=20
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prefetch_on_access=false
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prefetcher=Null
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response_latency=20
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size=2097152
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system=system
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tags=system.cpu.l2cache.tags
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tgts_per_mshr=12
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu.toL2Bus.master[0]
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mem_side=system.membus.slave[1]
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[system.cpu.l2cache.tags]
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type=LRU
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assoc=8
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block_size=64
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clk_domain=system.cpu_clk_domain
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hit_latency=20
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size=2097152
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[system.cpu.toL2Bus]
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type=CoherentBus
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clk_domain=system.cpu_clk_domain
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header_cycles=1
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system=system
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use_default_range=false
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width=32
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master=system.cpu.l2cache.cpu_side
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slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
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[system.cpu.tracer]
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type=ExeTracer
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[system.cpu.workload]
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type=LiveProcess
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cmd=hello
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cwd=
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egid=100
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env=
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errout=cerr
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euid=100
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executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello
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gid=100
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input=cin
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max_stack_size=67108864
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output=cout
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pid=100
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ppid=99
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simpoint=0
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system=system
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uid=100
|
|
|
|
[system.cpu_clk_domain]
|
|
type=SrcClockDomain
|
|
clock=500
|
|
voltage_domain=system.voltage_domain
|
|
|
|
[system.membus]
|
|
type=CoherentBus
|
|
clk_domain=system.clk_domain
|
|
header_cycles=1
|
|
system=system
|
|
use_default_range=false
|
|
width=8
|
|
master=system.physmem.port
|
|
slave=system.system_port system.cpu.l2cache.mem_side
|
|
|
|
[system.physmem]
|
|
type=SimpleDRAM
|
|
activation_limit=4
|
|
addr_mapping=RaBaChCo
|
|
banks_per_rank=8
|
|
burst_length=8
|
|
channels=1
|
|
clk_domain=system.clk_domain
|
|
conf_table_reported=true
|
|
device_bus_width=8
|
|
device_rowbuffer_size=1024
|
|
devices_per_rank=8
|
|
in_addr_map=true
|
|
mem_sched_policy=frfcfs
|
|
null=false
|
|
page_policy=open
|
|
range=0:134217727
|
|
ranks_per_channel=2
|
|
read_buffer_size=32
|
|
static_backend_latency=10000
|
|
static_frontend_latency=10000
|
|
tBURST=5000
|
|
tCL=13750
|
|
tRCD=13750
|
|
tREFI=7800000
|
|
tRFC=300000
|
|
tRP=13750
|
|
tWTR=7500
|
|
tXAW=40000
|
|
write_buffer_size=32
|
|
write_thresh_perc=70
|
|
port=system.membus.master[0]
|
|
|
|
[system.voltage_domain]
|
|
type=VoltageDomain
|
|
voltage=1.000000
|
|
|