b6d21b7a34
arch/mips/isa/decoder.isa:
Code for di,ei,seb,seh,clz,and clo ....
Every instruction has a format now (of course these are initial formats are still subject to change!)
arch/mips/isa/formats/branch.isa:
Format Branch in MIPS similar to Alpha Format
--HG--
extra : convert_revision : 2118a1d9668610b1e9f1dea66d878b7b36c1ac7e
67 lines
1.9 KiB
Plaintext
67 lines
1.9 KiB
Plaintext
////////////////////////////////////////////////////////////////////
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//
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// Branch instructions
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//
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output header {{
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/**
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* Base class for integer operations.
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*/
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class Branch : public MipsStaticInst
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{
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protected:
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/// Constructor
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Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return "Disassembly of integer instruction\n";
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}
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}};
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def template BranchExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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//Attempt to execute the instruction
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try
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{
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checkPriv;
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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}
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//If we have an exception for some reason,
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//deal with it
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catch(MipsException except)
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{
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//Deal with exception
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return No_Fault;
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}
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//Write the resulting state to the execution context
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%(op_wb)s;
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return No_Fault;
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}
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}};
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def format CondBranch(code) {{
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code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n';
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iop = InstObjParams(name, Name, 'Branch', CodeBlock(code),
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('IsDirectControl', 'IsCondControl'))
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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