b00949d88b
This patch removes the assumption on having on single instance of PhysicalMemory, and enables a distributed memory where the individual memories in the system are each responsible for a single contiguous address range. All memories inherit from an AbstractMemory that encompasses the basic behaviuor of a random access memory, and provides untimed access methods. What was previously called PhysicalMemory is now SimpleMemory, and a subclass of AbstractMemory. All future types of memory controllers should inherit from AbstractMemory. To enable e.g. the atomic CPU and RubyPort to access the now distributed memory, the system has a wrapper class, called PhysicalMemory that is aware of all the memories in the system and their associated address ranges. This class thus acts as an infinitely-fast bus and performs address decoding for these "shortcut" accesses. Each memory can specify that it should not be part of the global address map (used e.g. by the functional memories by some testers). Moreover, each memory can be configured to be reported to the OS configuration table, useful for populating ATAG structures, and any potential ACPI tables. Checkpointing support currently assumes that all memories have the same size and organisation when creating and resuming from the checkpoint. A future patch will enable a more flexible re-organisation. --HG-- rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py rename : src/mem/physical.cc => src/mem/abstract_mem.cc rename : src/mem/physical.hh => src/mem/abstract_mem.hh rename : src/mem/physical.cc => src/mem/simple_mem.cc rename : src/mem/physical.hh => src/mem/simple_mem.hh
180 lines
6.1 KiB
Python
180 lines
6.1 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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# Brad Beckmann
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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import os, optparse, sys
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addToPath('../common')
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addToPath('../ruby')
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import Options
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import Ruby
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# Get paths we might need. It's expected this file is in m5/configs/example.
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config_path = os.path.dirname(os.path.abspath(__file__))
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config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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parser.add_option("-l", "--maxloads", metavar="N", default=0,
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help="Stop after N loads")
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parser.add_option("--progress", type="int", default=1000,
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metavar="NLOADS",
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help="Progress message interval "
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"[default: %default]")
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parser.add_option("--num-dmas", type="int", default=0, help="# of dma testers")
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parser.add_option("--functional", type="int", default=0,
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help="percentage of accesses that should be functional")
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parser.add_option("--suppress-func-warnings", action="store_true",
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help="suppress warnings when functional accesses fail")
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#
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# Add the ruby specific and protocol specific options
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#
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Ruby.define_options(parser)
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execfile(os.path.join(config_root, "common", "Options.py"))
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(options, args) = parser.parse_args()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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#
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options.l1d_size="256B"
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options.l1i_size="256B"
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options.l2_size="512B"
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options.l3_size="1kB"
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options.l1d_assoc=2
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options.l1i_assoc=2
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options.l2_assoc=2
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options.l3_assoc=2
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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block_size = 64
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if options.num_cpus > block_size:
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print "Error: Number of testers %d limited to %d because of false sharing" \
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% (options.num_cpus, block_size)
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sys.exit(1)
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#
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# Currently ruby does not support atomic or uncacheable accesses
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#
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cpus = [ MemTest(atomic = False,
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max_loads = options.maxloads,
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issue_dmas = False,
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percent_functional = options.functional,
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percent_uncacheable = 0,
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progress_interval = options.progress,
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suppress_func_warnings = options.suppress_func_warnings) \
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for i in xrange(options.num_cpus) ]
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system = System(cpu = cpus,
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funcmem = SimpleMemory(in_addr_map = False),
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physmem = SimpleMemory())
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if options.num_dmas > 0:
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dmas = [ MemTest(atomic = False,
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max_loads = options.maxloads,
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issue_dmas = True,
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percent_functional = 0,
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percent_uncacheable = 0,
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progress_interval = options.progress,
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suppress_func_warnings =
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not options.suppress_func_warnings) \
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for i in xrange(options.num_dmas) ]
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system.dma_devices = dmas
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else:
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dmas = []
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dma_ports = []
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for (i, dma) in enumerate(dmas):
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dma_ports.append(dma.test)
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Ruby.create_system(options, system, dma_ports = dma_ports)
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#
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# The tester is most effective when randomization is turned on and
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# artifical delay is randomly inserted on messages
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#
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system.ruby.randomization = True
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assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
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for (i, cpu) in enumerate(cpus):
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#
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# Tie the cpu memtester ports to the correct system ports
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#
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cpu.test = system.ruby._cpu_ruby_ports[i].slave
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cpu.functional = system.funcmem.port
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#
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# Since the memtester is incredibly bursty, increase the deadlock
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# threshold to 5 million cycles
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#
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system.ruby._cpu_ruby_ports[i].deadlock_threshold = 5000000
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#
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# Ruby doesn't need the backing image of memory when running with
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# the tester.
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#
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system.ruby._cpu_ruby_ports[i].access_phys_mem = False
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for (i, dma) in enumerate(dmas):
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#
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# Tie the dma memtester ports to the correct functional port
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# Note that the test port has already been connected to the dma_sequencer
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#
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dma.functional = system.funcmem.port
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# -----------------------
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# run simulation
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# -----------------------
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root = Root( full_system = False, system = system )
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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# instantiate configuration
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m5.instantiate()
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# simulate until program terminates
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exit_event = m5.simulate(options.maxtick)
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print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
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