74553c7d3f
This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
709 lines
80 KiB
Text
709 lines
80 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.139913 # Number of seconds simulated
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sim_ticks 139912878500 # Number of ticks simulated
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final_tick 139912878500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 81894 # Simulator instruction rate (inst/s)
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host_op_rate 81894 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 28740964 # Simulator tick rate (ticks/s)
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host_mem_usage 231128 # Number of bytes of host memory used
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host_seconds 4868.07 # Real time elapsed on the host
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sim_insts 398664595 # Number of instructions simulated
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sim_ops 398664595 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
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system.physmem.bytes_read::total 468992 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 214976 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 214976 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1536499 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1815530 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 3352029 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1536499 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1536499 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1536499 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1815530 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 3352029 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 7328 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 468992 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 468992 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 507 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 643 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 444 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 597 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 448 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 451 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 505 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 513 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 423 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 395 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 336 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 304 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 416 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 534 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 441 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 371 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 139912806500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 7328 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 4704 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 1856 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 185 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 702 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 659.145299 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 261.737271 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 1246.496021 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64-65 193 27.49% 27.49% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-129 99 14.10% 41.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192-193 67 9.54% 51.14% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-257 56 7.98% 59.12% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320-321 35 4.99% 64.10% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-385 20 2.85% 66.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448-449 23 3.28% 70.23% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-513 21 2.99% 73.22% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576-577 15 2.14% 75.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-641 12 1.71% 77.07% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704-705 9 1.28% 78.35% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-769 4 0.57% 78.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::832-833 12 1.71% 80.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-897 8 1.14% 81.77% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::960-961 4 0.57% 82.34% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1025 5 0.71% 83.05% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1088-1089 15 2.14% 85.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1152-1153 5 0.71% 85.90% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1216-1217 6 0.85% 86.75% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1280-1281 1 0.14% 86.89% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1344-1345 4 0.57% 87.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1408-1409 4 0.57% 88.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1472-1473 4 0.57% 88.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1536-1537 3 0.43% 89.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1600-1601 6 0.85% 89.89% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1664-1665 6 0.85% 90.74% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1728-1729 2 0.28% 91.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1792-1793 3 0.43% 91.45% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1856-1857 2 0.28% 91.74% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1920-1921 1 0.14% 91.88% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1984-1985 3 0.43% 92.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.59% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2112-2113 4 0.57% 93.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2176-2177 2 0.28% 93.45% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2240-2241 2 0.28% 93.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2304-2305 1 0.14% 93.87% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2368-2369 2 0.28% 94.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2496-2497 3 0.43% 94.59% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2560-2561 2 0.28% 94.87% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2688-2689 3 0.43% 95.30% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2752-2753 1 0.14% 95.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2816-2817 1 0.14% 95.58% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2944-2945 1 0.14% 95.87% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.01% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3264-3265 2 0.28% 96.30% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.58% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4032-4033 2 0.28% 96.87% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4160-4161 1 0.14% 97.01% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4224-4225 1 0.14% 97.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4480-4481 1 0.14% 97.29% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4544-4545 1 0.14% 97.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.58% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::4992-4993 1 0.14% 97.72% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5312-5313 1 0.14% 97.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5632-5633 1 0.14% 98.01% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::5888-5889 1 0.14% 98.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::6208-6209 1 0.14% 98.29% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::6400-6401 1 0.14% 98.43% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::6464-6465 1 0.14% 98.58% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::6592-6593 1 0.14% 98.72% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7232-7233 1 0.14% 98.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::7296-7297 1 0.14% 99.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::8192-8193 7 1.00% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 702 # Bytes accessed per row activation
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system.physmem.totQLat 37727500 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 172831250 # Sum of mem lat for all requests
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system.physmem.totBusLat 36640000 # Total cycles spent in databus access
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system.physmem.totBankLat 98463750 # Total cycles spent in bank access
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system.physmem.avgQLat 5148.40 # Average queueing delay per request
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system.physmem.avgBankLat 13436.65 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 23585.05 # Average memory access latency
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system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.03 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.00 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 6626 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 19092904.82 # Average gap between requests
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system.membus.throughput 3352029 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 4183 # Transaction distribution
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system.membus.trans_dist::ReadResp 4183 # Transaction distribution
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system.membus.trans_dist::ReadExReq 3145 # Transaction distribution
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system.membus.trans_dist::ReadExResp 3145 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side 14656 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count 14656 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 468992 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size 468992 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 468992 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 8784000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 68408750 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.branchPred.lookups 53489761 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 30685482 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 32882438 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 15212539 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 46.263416 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions.
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 94754611 # DTB read hits
|
|
system.cpu.dtb.read_misses 21 # DTB read misses
|
|
system.cpu.dtb.read_acv 0 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 94754632 # DTB read accesses
|
|
system.cpu.dtb.write_hits 73521122 # DTB write hits
|
|
system.cpu.dtb.write_misses 35 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 73521157 # DTB write accesses
|
|
system.cpu.dtb.data_hits 168275733 # DTB hits
|
|
system.cpu.dtb.data_misses 56 # DTB misses
|
|
system.cpu.dtb.data_acv 0 # DTB access violations
|
|
system.cpu.dtb.data_accesses 168275789 # DTB accesses
|
|
system.cpu.itb.fetch_hits 48611325 # ITB hits
|
|
system.cpu.itb.fetch_misses 44520 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 48655845 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 215 # Number of system calls
|
|
system.cpu.numCycles 279825758 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.branch_predictor.predictedTaken 29230506 # Number of Branches Predicted As Taken (True).
|
|
system.cpu.branch_predictor.predictedNotTaken 24259255 # Number of Branches Predicted As Not Taken (False).
|
|
system.cpu.regfile_manager.intRegFileReads 280386575 # Number of Reads from Int. Register File
|
|
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
|
|
system.cpu.regfile_manager.intRegFileAccesses 439722434 # Total Accesses (Read+Write) to the Int. Register File
|
|
system.cpu.regfile_manager.floatRegFileReads 119631956 # Number of Reads from FP Register File
|
|
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
|
|
system.cpu.regfile_manager.floatRegFileAccesses 219828437 # Total Accesses (Read+Write) to the FP Register File
|
|
system.cpu.regfile_manager.regForwards 100484572 # Number of Registers Read Through Forwarding Logic
|
|
system.cpu.agen_unit.agens 168485322 # Number of Address Generations
|
|
system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken.
|
|
system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken).
|
|
system.cpu.execution_unit.mispredicted 15149000 # Number of Branches Incorrectly Predicted
|
|
system.cpu.execution_unit.predicted 29438551 # Number of Branches Incorrectly Predicted
|
|
system.cpu.execution_unit.mispredictPct 33.975851 # Percentage of Incorrect Branches Predicts
|
|
system.cpu.execution_unit.executions 205475782 # Number of Instructions Executed.
|
|
system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed
|
|
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
|
|
system.cpu.contextSwitches 1 # Number of context switches
|
|
system.cpu.threadCycles 279401420 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
|
|
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
|
system.cpu.timesIdled 7883 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 13519017 # Number of cycles cpu's stages were not processed
|
|
system.cpu.runCycles 266306741 # Number of cycles cpu stages are processed.
|
|
system.cpu.activity 95.168773 # Percentage of cycles cpu is active
|
|
system.cpu.comLoads 94754489 # Number of Load instructions committed
|
|
system.cpu.comStores 73520729 # Number of Store instructions committed
|
|
system.cpu.comBranches 44587532 # Number of Branches instructions committed
|
|
system.cpu.comNops 23089775 # Number of Nop instructions committed
|
|
system.cpu.comNonSpec 215 # Number of Non-Speculative instructions committed
|
|
system.cpu.comInts 112239074 # Number of Integer instructions committed
|
|
system.cpu.comFloats 50439198 # Number of Floating Point instructions committed
|
|
system.cpu.committedInsts 398664595 # Number of Instructions committed (Per-Thread)
|
|
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
|
|
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
|
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
|
|
system.cpu.cpi 0.701908 # CPI: Cycles Per Instruction (Per-Thread)
|
|
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
|
system.cpu.cpi_total 0.701908 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.424689 # IPC: Instructions Per Cycle (Per-Thread)
|
|
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
|
system.cpu.ipc_total 1.424689 # IPC: Total IPC of All Threads
|
|
system.cpu.stage0.idleCycles 78078009 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage0.runCycles 201747749 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage0.utilization 72.097633 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage1.idleCycles 107174029 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage1.runCycles 172651729 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage1.utilization 61.699727 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage2.idleCycles 102610556 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage2.runCycles 177215202 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage2.utilization 63.330554 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage3.idleCycles 181081179 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage3.runCycles 98744579 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage3.utilization 35.287880 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage4.idleCycles 90357849 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage4.runCycles 189467909 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage4.utilization 67.709245 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.icache.replacements 1975 # number of replacements
|
|
system.cpu.icache.tagsinuse 1830.982662 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 48606794 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 12453.700743 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1830.982662 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.894035 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.894035 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 48606794 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 48606794 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 48606794 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 48606794 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 48606794 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 48606794 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 4531 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 4531 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 4531 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 4531 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 4531 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 4531 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 268165000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 268165000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 268165000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 268165000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 268165000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 268165000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 48611325 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 48611325 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 48611325 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 48611325 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 48611325 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 48611325 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59184.506731 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 59184.506731 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 59184.506731 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 59184.506731 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 59184.506731 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 59184.506731 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 326 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 108.666667 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 628 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 628 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 628 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 628 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 628 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 628 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 234852500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 234852500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 234852500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 234852500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 234852500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 234852500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60172.303356 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60172.303356 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60172.303356 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 60172.303356 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60172.303356 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 60172.303356 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 3981449 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 3205 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 3205 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 7806 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 8953 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count 16759 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 249792 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 307264 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size 557056 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 557056 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 5854500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 6228499 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 3906.975758 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.159635 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 370.554458 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 2908.829780 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 627.591520 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.088770 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.019153 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.119231 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 544 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 727 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 544 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 727 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3359 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 824 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 4183 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 3145 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 3145 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3359 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 7328 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3359 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 7328 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 225463500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 58932500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 284396000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 213301500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 213301500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 225463500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 272234000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 497697500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 225463500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 272234000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 497697500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3903 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 4850 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 3903 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 8055 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 3903 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 8055 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.860620 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.870116 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.862474 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.981279 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.860620 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.909745 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.860620 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.909745 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67122.208991 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71520.024272 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67988.524982 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67822.416534 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67822.416534 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67122.208991 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68590.073066 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 67917.235262 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67122.208991 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68590.073066 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 67917.235262 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3359 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 824 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4183 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3359 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 7328 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3359 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 7328 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 183879500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 48740750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 232620250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 174684500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 174684500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 183879500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 223425250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 407304750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 183879500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 223425250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 407304750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870116 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.862474 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981279 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.909745 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.860620 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.909745 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54742.334028 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59151.395631 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55610.865408 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55543.561208 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55543.561208 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54742.334028 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56292.579995 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55581.980076 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54742.334028 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56292.579995 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55581.980076 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 764 # number of replacements
|
|
system.cpu.dcache.tagsinuse 3284.992544 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 168254254 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 40523.664258 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 3284.992544 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.802000 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.802000 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 73501073 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 73501073 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 168254254 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 168254254 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 168254254 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 168254254 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1308 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1308 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 19656 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 19656 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 20964 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 20964 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 20964 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 20964 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 84017000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 84017000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1065172500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 1065172500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 1149189500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 1149189500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 1149189500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 1149189500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 94754489 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 94754489 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 168275218 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 168275218 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 168275218 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 168275218 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000014 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000267 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000267 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000125 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000125 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000125 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000125 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 64233.180428 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 64233.180428 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54190.705128 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 54190.705128 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 54817.282007 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 54817.282007 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54817.282007 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 54817.282007 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 28818 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 562 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 51.277580 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 649 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 358 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 358 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16454 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 16454 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 16812 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 16812 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 16812 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 16812 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61415001 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 61415001 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 217011500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 217011500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 278426501 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 278426501 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 278426501 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 278426501 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64647.369474 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64647.369474 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67773.735166 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67773.735166 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67058.405829 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67058.405829 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67058.405829 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67058.405829 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|