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gem5/src/cpu/minor
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Andreas Sandberg f73b05431a cpu: Fix Minor drain issues when switched out 
The Minor CPU currently doesn't drain properly when it is switched
out. This happens because Fetch 1 expects to be in the FetchHalted
state when it is drained. However, because the CPU is switched out, it
is stuck in the FetchWaitingForPC state. Fix this by ignoring drain
requests and returning DrainState::Drained from MinorCPU::drain() if
the CPU is switched out. This is always safe since a switched out CPU,
by definition, doesn't have any instructions in flight.
2015-07-31 17:04:59 +01:00
..
activity.cc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
activity.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
buffers.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
cpu.cc cpu: Fix Minor drain issues when switched out 2015-07-31 17:04:59 +01:00
cpu.hh sim: Refactor and simplify the drain API 2015-07-07 09:51:05 +01:00
decode.cc arm: Fixes based on UBSan and static analysis 2014-11-14 03:53:51 -05:00
decode.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
dyn_inst.cc revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
dyn_inst.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
exec_context.hh revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
execute.cc cpu: Fix a bug in counting issued instructions in MinorCPU 2015-05-26 03:21:37 -04:00
execute.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
fetch1.cc mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
fetch1.hh mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
fetch2.cc arm: Fixes based on UBSan and static analysis 2014-11-14 03:53:51 -05:00
fetch2.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
func_unit.cc arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
func_unit.hh arch: Use const StaticInstPtr references where possible 2014-09-27 09:08:36 -04:00
lsq.cc mem, cpu: Add a separate flag for strictly ordered memory 2015-05-05 03:22:33 -04:00
lsq.hh mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
MinorCPU.py cpu: re-organizes the branch predictor structure. 2015-04-13 17:33:57 -05:00
pipe_data.cc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
pipe_data.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
pipeline.cc sim: Refactor and simplify the drain API 2015-07-07 09:51:05 +01:00
pipeline.hh sim: Refactor and simplify the drain API 2015-07-07 09:51:05 +01:00
SConscript cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
SConsopts arch, cpu: Factor out the ExecContext into a proper base class 2014-09-03 07:42:22 -04:00
scoreboard.cc revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
scoreboard.hh revert 5af8f40d8f2c 2015-07-28 01:58:04 -05:00
stats.cc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
stats.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
trace.hh cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00