959 lines
109 KiB
Plaintext
959 lines
109 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000023 # Number of seconds simulated
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sim_ticks 22762000 # Number of ticks simulated
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final_tick 22762000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 3472 # Simulator instruction rate (inst/s)
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host_op_rate 3472 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 15849922 # Simulator tick rate (ticks/s)
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host_mem_usage 223436 # Number of bytes of host memory used
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host_seconds 1.44 # Real time elapsed on the host
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sim_insts 4986 # Number of instructions simulated
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sim_ops 4986 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 21120 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
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system.physmem.bytes_read::total 30144 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 21120 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 21120 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 330 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 471 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 927862227 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 396450224 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1324312451 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 927862227 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 927862227 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 927862227 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 396450224 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1324312451 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 471 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 471 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 30144 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 30144 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 29 # Per bank write bursts
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system.physmem.perBankRdBursts::1 0 # Per bank write bursts
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system.physmem.perBankRdBursts::2 1 # Per bank write bursts
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system.physmem.perBankRdBursts::3 0 # Per bank write bursts
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system.physmem.perBankRdBursts::4 7 # Per bank write bursts
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system.physmem.perBankRdBursts::5 3 # Per bank write bursts
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system.physmem.perBankRdBursts::6 13 # Per bank write bursts
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system.physmem.perBankRdBursts::7 53 # Per bank write bursts
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system.physmem.perBankRdBursts::8 59 # Per bank write bursts
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system.physmem.perBankRdBursts::9 76 # Per bank write bursts
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system.physmem.perBankRdBursts::10 43 # Per bank write bursts
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system.physmem.perBankRdBursts::11 20 # Per bank write bursts
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system.physmem.perBankRdBursts::12 51 # Per bank write bursts
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system.physmem.perBankRdBursts::13 29 # Per bank write bursts
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system.physmem.perBankRdBursts::14 80 # Per bank write bursts
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system.physmem.perBankRdBursts::15 7 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 22674500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 471 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 277 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 104 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 262.153846 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 181.184943 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 253.583818 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 28 26.92% 26.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 35 33.65% 60.58% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 18 17.31% 77.88% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 10 9.62% 87.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 3 2.88% 90.38% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 2 1.92% 92.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1 0.96% 93.27% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1 0.96% 94.23% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 6 5.77% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 104 # Bytes accessed per row activation
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system.physmem.totQLat 5218000 # Total ticks spent queuing
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system.physmem.totMemAccLat 14049250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 2355000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 11078.56 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 29828.56 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 1324.31 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 1324.31 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 10.35 # Data bus utilization in percentage
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system.physmem.busUtilRead 10.35 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 356 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 48141.19 # Average gap between requests
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system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 491400 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 9465705 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 1196250 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 12369120 # Total energy per rank (pJ)
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system.physmem_0.averagePower 781.248697 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 1950500 # Time in different power states
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system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
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system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_0.memoryStateTime::ACT 13375750 # Time in different power states
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system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.physmem_1.actEnergy 514080 # Energy for activate commands per rank (pJ)
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system.physmem_1.preEnergy 280500 # Energy for precharge commands per rank (pJ)
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system.physmem_1.readEnergy 2184000 # Energy for read commands per rank (pJ)
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system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
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system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
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system.physmem_1.actBackEnergy 10729395 # Energy for active background per rank (pJ)
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system.physmem_1.preBackEnergy 87750 # Energy for precharge background per rank (pJ)
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system.physmem_1.totalEnergy 14812845 # Total energy per rank (pJ)
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system.physmem_1.averagePower 935.597347 # Core power per rank (mW)
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system.physmem_1.memoryStateTime::IDLE 284750 # Time in different power states
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system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
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system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem_1.memoryStateTime::ACT 15222250 # Time in different power states
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system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.cpu.branchPred.lookups 2110 # Number of BP lookups
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system.cpu.branchPred.condPredicted 1371 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 423 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 1629 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 525 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 32.228361 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 280 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions.
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 7 # Number of system calls
|
|
system.cpu.numCycles 45525 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 8934 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 12895 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 2110 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 805 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 4920 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.PendingTrapStallCycles 192 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.CacheLines 2026 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 14478 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.890662 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.186824 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 11164 77.11% 77.11% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 1470 10.15% 87.26% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 124 0.86% 88.12% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 160 1.11% 89.23% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 283 1.95% 91.18% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 94 0.65% 91.83% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 128 0.88% 92.71% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 113 0.78% 93.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 942 6.51% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 14478 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.046348 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.283251 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 8487 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 2706 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 2773 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 391 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 174 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 11880 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 172 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 391 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 8645 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 502 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 1002 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 2724 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 1214 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 11398 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 231 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 967 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 6879 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 13412 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 13162 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 3597 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 13 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 290 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 2474 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 1168 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 8940 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 8204 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 35 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 3964 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 1790 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 14478 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.566653 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.310295 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 11167 77.13% 77.13% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 1314 9.08% 86.21% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 734 5.07% 91.28% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 423 2.92% 94.20% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 344 2.38% 96.57% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 310 2.14% 98.72% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 102 0.70% 99.42% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 57 0.39% 99.81% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 27 0.19% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 14478 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 9 4.59% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 129 65.82% 70.41% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 58 29.59% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 4822 58.78% 58.78% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.84% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 2303 28.07% 86.93% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 1072 13.07% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 8204 # Type of FU issued
|
|
system.cpu.iq.rate 0.180209 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 196 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.023891 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 31113 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 12922 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 7408 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 8398 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 82 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1342 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 267 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 391 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 464 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 10483 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 2474 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 1168 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 12 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 96 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 348 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 444 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 7875 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 2160 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 329 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 1532 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 3217 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 1365 # Number of branches executed
|
|
system.cpu.iew.exec_stores 1057 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.172982 # Inst execution rate
|
|
system.cpu.iew.wb_sent 7509 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 7410 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 2869 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 4254 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.162768 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.674424 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 4860 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 382 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 13623 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.412758 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.228786 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 11456 84.09% 84.09% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 871 6.39% 90.49% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 510 3.74% 94.23% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 252 1.85% 96.08% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 148 1.09% 97.17% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 178 1.31% 98.47% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 65 0.48% 98.95% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 40 0.29% 99.24% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 103 0.76% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 13623 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 5623 # Number of instructions committed
|
|
system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 2033 # Number of memory references committed
|
|
system.cpu.commit.loads 1132 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 883 # Number of branches committed
|
|
system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 4942 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 85 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 637 11.33% 11.33% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 2949 52.45% 63.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 2 0.04% 63.81% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.81% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 1132 20.13% 83.98% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 5623 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 103 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 23990 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 21831 # The number of ROB writes
|
|
system.cpu.timesIdled 267 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 31047 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 4986 # Number of Instructions Simulated
|
|
system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 9.130566 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 9.130566 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.109522 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.109522 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 10639 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 5201 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 165 # number of misc regfile reads
|
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 91.212769 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 2418 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 17.148936 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 91.212769 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.022269 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.022269 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 5997 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 5997 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1862 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1862 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 2418 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 2418 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 2418 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 2418 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 510 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12038750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 12038750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 24387249 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 24387249 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 36425999 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 36425999 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 36425999 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 36425999 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 2027 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 2027 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2928 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2928 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2928 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2928 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081401 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.081401 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.174180 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.174180 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.174180 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.174180 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72962.121212 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 72962.121212 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70687.678261 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 70687.678261 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 71423.527451 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 71423.527451 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 71423.527451 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 71423.527451 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7833500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7833500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4084749 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4084749 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11918249 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 11918249 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11918249 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 11918249 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044894 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044894 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048156 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.048156 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048156 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.048156 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86082.417582 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86082.417582 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81694.980000 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81694.980000 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84526.588652 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 84526.588652 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84526.588652 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 84526.588652 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 17 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 158.205778 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 333 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 4.735736 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 158.205778 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.077249 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.077249 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.154297 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 4385 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 4385 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 1577 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 449 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 449 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 449 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 449 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 449 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 449 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34003000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 34003000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 34003000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 34003000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 34003000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 34003000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 2026 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 2026 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 2026 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.221619 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.221619 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.221619 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.221619 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.221619 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.221619 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75730.512249 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 75730.512249 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75730.512249 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 75730.512249 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75730.512249 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 75730.512249 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 116 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 116 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 116 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 116 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 333 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 333 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 333 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26389500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 26389500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26389500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 26389500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26389500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 26389500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.164363 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.164363 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.164363 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79247.747748 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79247.747748 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79247.747748 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 79247.747748 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79247.747748 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 79247.747748 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 218.150435 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.007126 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.168468 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 57.981967 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004888 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001769 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.006657 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 4263 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 4263 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 3 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 330 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 421 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 330 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 471 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 330 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 471 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26025000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7738500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 33763500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4034000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4034000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 26025000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 11772500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 37797500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 26025000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 11772500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 37797500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 333 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 333 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 474 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 333 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 474 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.990991 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.992925 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990991 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.993671 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990991 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.993671 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78863.636364 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85038.461538 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 80198.337292 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80680 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80680 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78863.636364 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83492.907801 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 80249.469214 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78863.636364 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83492.907801 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 80249.469214 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 330 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 421 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 330 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 471 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21894000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6598000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28492000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3411000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3411000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21894000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10009000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 31903000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21894000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10009000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 31903000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992925 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.993671 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.993671 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66345.454545 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72505.494505 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67676.959620 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68220 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68220 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66345.454545 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70985.815603 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67734.607219 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66345.454545 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70985.815603 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67734.607219 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 666 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 948 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21312 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 30336 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 474 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 474 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 569000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 233500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadReq 421 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 421 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 50 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 50 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 471 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 471 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 598000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2506000 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 11.0 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|