248 lines
28 KiB
Plaintext
248 lines
28 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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host_inst_rate 981553 # Simulator instruction rate (inst/s)
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host_mem_usage 203224 # Number of bytes of host memory used
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host_seconds 248.41 # Real time elapsed on the host
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host_tick_rate 1462749007 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 243829010 # Number of instructions simulated
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sim_seconds 0.363364 # Number of seconds simulated
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sim_ticks 363364127000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 82219469 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 13897.517462 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11897.517462 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 81326673 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 12407648000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 892796 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 10622056000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 892796 # number of ReadReq MSHR misses
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system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
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system.cpu.dcache.SwapReq_avg_miss_latency 25000 # average SwapReq miss latency
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system.cpu.dcache.SwapReq_avg_mshr_miss_latency 23000 # average SwapReq mshr miss latency
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system.cpu.dcache.SwapReq_hits 3878 # number of SwapReq hits
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system.cpu.dcache.SwapReq_miss_latency 200000 # number of SwapReq miss cycles
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system.cpu.dcache.SwapReq_miss_rate 0.002059 # miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_misses 8 # number of SwapReq misses
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system.cpu.dcache.SwapReq_mshr_miss_latency 184000 # number of SwapReq MSHR miss cycles
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system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses
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system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 22901836 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 25000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 22806941 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 2372375000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.004144 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 94895 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 2182585000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.004144 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 94895 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 110.894471 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 105121305 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 14964.217554 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 12964.217554 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 104133614 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 14780023000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.009396 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 987691 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 12804641000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.009396 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 987691 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 105121305 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 14964.217554 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 12964.217554 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 104133614 # number of overall hits
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system.cpu.dcache.overall_miss_latency 14780023000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.009396 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 987691 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 12804641000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.009396 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 987691 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 935407 # number of replacements
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system.cpu.dcache.sampled_refs 939503 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 3566.459969 # Cycle average of tags in use
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system.cpu.dcache.total_refs 104185688 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 134193645000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 94807 # number of writebacks
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system.cpu.icache.ReadReq_accesses 244425341 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 24972.696246 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 22972.696246 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 244424462 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 21951000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 879 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 20193000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 879 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 278071.060296 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 244425341 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 24972.696246 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 22972.696246 # average overall mshr miss latency
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system.cpu.icache.demand_hits 244424462 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 21951000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
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system.cpu.icache.demand_misses 879 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 20193000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 879 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 244425341 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 24972.696246 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 22972.696246 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 244424462 # number of overall hits
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system.cpu.icache.overall_miss_latency 21951000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
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system.cpu.icache.overall_misses 879 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 20193000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 879 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.icache.replacements 25 # number of replacements
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system.cpu.icache.sampled_refs 879 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 716.846544 # Cycle average of tags in use
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system.cpu.icache.total_refs 244424462 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadExReq_accesses 46707 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 22000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 1027554000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 46707 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 513777000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 46707 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 893675 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 22000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 826023 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 1488344000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.075701 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 67652 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 744172000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.075701 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 67652 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 48196 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 22000 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 1060312000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 48196 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530156000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 48196 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 94807 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_miss_rate 1 # miss rate for Writeback accesses
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system.cpu.l2cache.Writeback_misses 94807 # number of Writeback misses
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system.cpu.l2cache.Writeback_mshr_miss_rate 1 # mshr miss rate for Writeback accesses
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system.cpu.l2cache.Writeback_mshr_misses 94807 # number of Writeback MSHR misses
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system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 48.779815 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 940382 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 22000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 826023 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 2515898000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.121609 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 114359 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 1257949000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.121609 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 114359 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 940382 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 22000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 826023 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 2515898000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.121609 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 114359 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 1257949000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.121609 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 114359 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.l2cache.replacements 829 # number of replacements
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system.cpu.l2cache.sampled_refs 11345 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 8106.936507 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 553407 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
|
system.cpu.numCycles 726728254 # number of cpu cycles simulated
|
|
system.cpu.num_insts 243829010 # Number of instructions executed
|
|
system.cpu.num_refs 105710359 # Number of memory references
|
|
system.cpu.workload.PROG:num_syscalls 428 # Number of system calls
|
|
|
|
---------- End Simulation Statistics ----------
|