gem5/src/arch
Ali Saidi ba14d6d0e1 Bug fixes in the TLB
Make our replacement algorithm same as legion (although not same as the spec)
itb should be 64 entries not 48

src/arch/sparc/tlb.cc:
    Bug fixes in the TLB
    Make our replacement algorithm same as legion (although not same as the spec)
src/arch/sparc/tlb.hh:
    Make our replacement algorithm same as legion (although not same as the spec)
src/python/m5/objects/SparcTLB.py:
    itb should be 64 entries too

--HG--
extra : convert_revision : 1b5cb3597091e3cfe293e94f6f2219b1e621c35f
2006-12-27 14:38:07 -05:00
..
alpha Merge zizzer:/bk/sparcfs 2006-12-15 13:27:53 -05:00
mips Merge zizzer:/bk/sparcfs 2006-12-15 13:27:53 -05:00
sparc Bug fixes in the TLB 2006-12-27 14:38:07 -05:00
isa_parser.py Merge zizzer:/bk/newmem 2006-12-12 21:19:51 -05:00
isa_specific.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
SConscript Add support for mmapped iprs to atomic cpu 2006-11-29 17:11:10 -05:00