207 lines
23 KiB
Text
207 lines
23 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1718028 # Simulator instruction rate (inst/s)
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host_mem_usage 214564 # Number of bytes of host memory used
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host_seconds 127.24 # Real time elapsed on the host
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host_tick_rate 1972277446 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 218595300 # Number of instructions simulated
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sim_seconds 0.250945 # Number of seconds simulated
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sim_ticks 250945484000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 56649600 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 55873.040752 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52873.040752 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 56649281 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 17823500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 319 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 16866500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 20515729 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 20514128 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 89656000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.000078 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 1601 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 84853000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000078 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 1601 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 40740.989968 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 77165329 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 55978.906250 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 77163409 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 107479500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 1920 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 101719500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 1920 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 77165329 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 55978.906250 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 52978.906250 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 77163409 # number of overall hits
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system.cpu.dcache.overall_miss_latency 107479500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 1920 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 101719500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 1920 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 27 # number of replacements
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system.cpu.dcache.sampled_refs 1894 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 1362.582924 # Cycle average of tags in use
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system.cpu.dcache.total_refs 77163435 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 2 # number of writebacks
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system.cpu.icache.ReadReq_accesses 173494366 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 39408.800341 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 36408.693799 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 173489673 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 184945500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 4693 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 170866000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000027 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 4693 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 36967.754741 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 173494366 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 39408.800341 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency
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system.cpu.icache.demand_hits 173489673 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 184945500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses
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system.cpu.icache.demand_misses 4693 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 170866000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 4693 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 173494366 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 39408.800341 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 36408.693799 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 173489673 # number of overall hits
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system.cpu.icache.overall_miss_latency 184945500 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses
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system.cpu.icache.overall_misses 4693 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 170866000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 4693 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 2835 # number of replacements
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system.cpu.icache.sampled_refs 4693 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1454.285546 # Cycle average of tags in use
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system.cpu.icache.total_refs 173489673 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadExReq_accesses 1575 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 81900000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 1575 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 5012 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52002.058917 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 1855 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 164170500 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.629888 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 3157 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 126280000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629888 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 3157 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 26 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 1352000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 26 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1040000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 26 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 0.592084 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 6587 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52001.373626 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 1855 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 246070500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.718385 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 4732 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 189280000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.718385 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 4732 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 6587 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52001.373626 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 1855 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 246070500 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.718385 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 4732 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 189280000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.718385 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 4732 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.sampled_refs 3133 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 2032.147267 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 1855 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 0 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 501890968 # number of cpu cycles simulated
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system.cpu.num_insts 218595300 # Number of instructions executed
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system.cpu.num_refs 77165298 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
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---------- End Simulation Statistics ----------
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