e0fdd86fd9
*** (1): get rid of expandForMT function MIPS is the only ISA that cares about having a piece of ISA state integrate multiple threads so add constants for MIPS and relieve the other ISAs from having to define this. Also, InOrder was the only core that was actively calling this function * * * (2): get rid of corespecific type The CoreSpecific type was used as a proxy to pass in HW specific params to a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense to not force every other ISA to use CoreSpecific as well use a special reset function to set it. That probably should go in a PowerOn reset fault anyway.
168 lines
6.2 KiB
C++
168 lines
6.2 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*/
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#ifndef __ARCH_MIPS_TYPES_HH__
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#define __ARCH_MIPS_TYPES_HH__
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#include "arch/generic/types.hh"
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#include "base/types.hh"
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namespace MipsISA
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{
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typedef uint32_t MachInst;
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typedef uint64_t ExtMachInst;
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typedef GenericISA::DelaySlotPCState<MachInst> PCState;
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typedef uint64_t LargestRead;
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//used in FP convert & round function
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enum ConvertType{
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SINGLE_TO_DOUBLE,
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SINGLE_TO_WORD,
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SINGLE_TO_LONG,
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DOUBLE_TO_SINGLE,
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DOUBLE_TO_WORD,
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DOUBLE_TO_LONG,
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LONG_TO_SINGLE,
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LONG_TO_DOUBLE,
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LONG_TO_WORD,
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LONG_TO_PS,
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WORD_TO_SINGLE,
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WORD_TO_DOUBLE,
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WORD_TO_LONG,
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WORD_TO_PS,
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PL_TO_SINGLE,
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PU_TO_SINGLE
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};
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//used in FP convert & round function
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enum RoundMode{
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RND_ZERO,
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RND_DOWN,
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RND_UP,
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RND_NEAREST
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};
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struct CoreSpecific {
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CoreSpecific()
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: CP0_IntCtl_IPTI(0), CP0_IntCtl_IPPCI(0), CP0_SrsCtl_HSS(0),
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CP0_PRId_CompanyOptions(0), CP0_PRId_CompanyID(0),
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CP0_PRId_ProcessorID(0), CP0_PRId_Revision(0),
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CP0_EBase_CPUNum(0), CP0_Config_BE(0), CP0_Config_AT(0),
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CP0_Config_AR(0), CP0_Config_MT(0), CP0_Config_VI(0),
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CP0_Config1_M(0), CP0_Config1_MMU(0), CP0_Config1_IS(0),
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CP0_Config1_IL(0), CP0_Config1_IA(0), CP0_Config1_DS(0),
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CP0_Config1_DL(0), CP0_Config1_DA(0), CP0_Config1_C2(false),
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CP0_Config1_MD(false), CP0_Config1_PC(false), CP0_Config1_WR(false),
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CP0_Config1_CA(false), CP0_Config1_EP(false), CP0_Config1_FP(false),
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CP0_Config2_M(false), CP0_Config2_TU(0), CP0_Config2_TS(0),
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CP0_Config2_TL(0), CP0_Config2_TA(0), CP0_Config2_SU(0),
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CP0_Config2_SS(0), CP0_Config2_SL(0), CP0_Config2_SA(0),
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CP0_Config3_M(false), CP0_Config3_DSPP(false), CP0_Config3_LPA(false),
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CP0_Config3_VEIC(false), CP0_Config3_VInt(false),
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CP0_Config3_SP(false), CP0_Config3_MT(false), CP0_Config3_SM(false),
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CP0_Config3_TL(false), CP0_WatchHi_M(false), CP0_PerfCtr_M(false),
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CP0_PerfCtr_W(false), CP0_PRId(0), CP0_Config(0), CP0_Config1(0),
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CP0_Config2(0), CP0_Config3(0)
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{ }
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// MIPS CP0 State - First individual variables
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// Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM,
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// Volume III (PRA)
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unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt
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unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt
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unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set
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unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options
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unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS)
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unsigned CP0_PRId_ProcessorID; // Page 105
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unsigned CP0_PRId_Revision; // Page 105
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unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor
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//system
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unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode
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unsigned CP0_Config_AT; //Page 109
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unsigned CP0_Config_AR; //Page 109
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unsigned CP0_Config_MT; //Page 109
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unsigned CP0_Config_VI; //Page 109
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unsigned CP0_Config1_M; // Page 110
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unsigned CP0_Config1_MMU; // Page 110
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unsigned CP0_Config1_IS; // Page 110
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unsigned CP0_Config1_IL; // Page 111
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unsigned CP0_Config1_IA; // Page 111
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unsigned CP0_Config1_DS; // Page 111
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unsigned CP0_Config1_DL; // Page 112
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unsigned CP0_Config1_DA; // Page 112
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bool CP0_Config1_C2; // Page 112
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bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32
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bool CP0_Config1_PC;// Page 112
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bool CP0_Config1_WR;// Page 113
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bool CP0_Config1_CA;// Page 113
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bool CP0_Config1_EP;// Page 113
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bool CP0_Config1_FP;// Page 113
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bool CP0_Config2_M; // Page 114
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unsigned CP0_Config2_TU;// Page 114
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unsigned CP0_Config2_TS;// Page 114
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unsigned CP0_Config2_TL;// Page 115
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unsigned CP0_Config2_TA;// Page 115
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unsigned CP0_Config2_SU;// Page 115
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unsigned CP0_Config2_SS;// Page 115
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unsigned CP0_Config2_SL;// Page 116
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unsigned CP0_Config2_SA;// Page 116
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bool CP0_Config3_M; //// Page 117
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bool CP0_Config3_DSPP;// Page 117
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bool CP0_Config3_LPA;// Page 117
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bool CP0_Config3_VEIC;// Page 118
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bool CP0_Config3_VInt; // Page 118
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bool CP0_Config3_SP;// Page 118
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bool CP0_Config3_MT;// Page 119
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bool CP0_Config3_SM;// Page 119
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bool CP0_Config3_TL;// Page 119
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bool CP0_WatchHi_M; // Page 124
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bool CP0_PerfCtr_M; // Page 130
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bool CP0_PerfCtr_W; // Page 130
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// Then, whole registers
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unsigned CP0_PRId;
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unsigned CP0_Config;
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unsigned CP0_Config1;
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unsigned CP0_Config2;
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unsigned CP0_Config3;
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};
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} // namespace MipsISA
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#endif
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