Matthias Jung 8723b08dbf misc: Coupling gem5 with SystemC TLM2.0 ... Transaction Level Modeling (TLM2.0) is widely used in industry for creating virtual platforms (IEEE 1666 SystemC). This patch contains a standard compliant implementation of an external gem5 port, that enables the usage of gem5 as a TLM initiator component in SystemC based virtual platforms. Both TLM coding paradigms loosely timed (b_transport) and aproximately timed (nb_transport) are supported. Compared to the original patch a TLM memory manager was added. Furthermore, the transaction object was removed and for each TLM payload a PacketPointer that points to the original gem5 packet is added as an TLM extension. For event handling single events are now created. Committed by: Nilay Vaish <nilay@cs.wisc.edu>		2015-08-03 23:08:40 -05:00
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Benchmarks.py	config: Specify OS type and release on command line	2015-03-19 04:06:14 -04:00
CacheConfig.py	mem: Allow read-only caches and check compliance	2015-07-03 10:14:39 -04:00
Caches.py	mem: Remove redundant is_top_level cache parameter	2015-07-03 10:14:43 -04:00
cpu2000.py	arm: Add support for ARMv8 (AArch64 & AArch32)	2014-01-24 15:29:34 -06:00
CpuConfig.py	kvm, arm: Add support for aarch64	2015-06-01 19:44:19 +01:00
FSConfig.py	config: Support full-system with SST's memory system	2015-04-08 15:56:06 -05:00
MemConfig.py	misc: Coupling gem5 with SystemC TLM2.0	2015-08-03 23:08:40 -05:00
O3_ARM_v7a.py	mem: Remove redundant is_top_level cache parameter	2015-07-03 10:14:43 -04:00
Options.py	misc: Coupling gem5 with SystemC TLM2.0	2015-08-03 23:08:40 -05:00
Simulation.py	config, cpu: fix progress interval for switched CPUs	2015-04-14 11:01:10 -05:00
SysPaths.py	config: expand '~' and '~user' in paths	2015-03-23 16:14:19 -07:00