992 lines
112 KiB
Plaintext
992 lines
112 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000024 # Number of seconds simulated
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sim_ticks 24229500 # Number of ticks simulated
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final_tick 24229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 46987 # Simulator instruction rate (inst/s)
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host_op_rate 46985 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 89318295 # Simulator tick rate (ticks/s)
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host_mem_usage 231368 # Number of bytes of host memory used
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host_seconds 0.27 # Real time elapsed on the host
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sim_insts 12745 # Number of instructions simulated
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sim_ops 12745 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 22464 # Number of bytes read from this memory
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system.physmem.bytes_read::total 62400 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 39936 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 39936 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 624 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 351 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 975 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1648238717 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 927134278 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 2575372996 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1648238717 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1648238717 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1648238717 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 927134278 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 2575372996 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 975 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 82 # Per bank write bursts
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system.physmem.perBankRdBursts::1 153 # Per bank write bursts
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system.physmem.perBankRdBursts::2 77 # Per bank write bursts
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system.physmem.perBankRdBursts::3 60 # Per bank write bursts
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system.physmem.perBankRdBursts::4 87 # Per bank write bursts
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system.physmem.perBankRdBursts::5 49 # Per bank write bursts
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system.physmem.perBankRdBursts::6 32 # Per bank write bursts
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system.physmem.perBankRdBursts::7 49 # Per bank write bursts
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system.physmem.perBankRdBursts::8 42 # Per bank write bursts
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system.physmem.perBankRdBursts::9 39 # Per bank write bursts
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system.physmem.perBankRdBursts::10 30 # Per bank write bursts
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system.physmem.perBankRdBursts::11 33 # Per bank write bursts
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system.physmem.perBankRdBursts::12 15 # Per bank write bursts
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system.physmem.perBankRdBursts::13 121 # Per bank write bursts
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system.physmem.perBankRdBursts::14 70 # Per bank write bursts
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system.physmem.perBankRdBursts::15 36 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 24081000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 975 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 344 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 370 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 169 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 70 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 217 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 271.926267 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 156.688517 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 360.951821 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64 92 42.40% 42.40% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128 33 15.21% 57.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192 21 9.68% 67.28% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256 20 9.22% 76.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320 3 1.38% 77.88% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384 8 3.69% 81.57% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448 3 1.38% 82.95% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512 4 1.84% 84.79% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::576 4 1.84% 86.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640 4 1.84% 88.48% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704 5 2.30% 90.78% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768 4 1.84% 92.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::832 2 0.92% 93.55% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896 2 0.92% 94.47% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::960 3 1.38% 95.85% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024 1 0.46% 96.31% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1408 2 0.92% 97.24% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1536 2 0.92% 98.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1600 1 0.46% 98.62% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1856 2 0.92% 99.54% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2304 1 0.46% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 217 # Bytes accessed per row activation
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system.physmem.totQLat 9442250 # Total ticks spent queuing
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system.physmem.totMemAccLat 31257250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers
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system.physmem.totBankLat 16940000 # Total ticks spent accessing banks
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system.physmem.avgQLat 9684.36 # Average queueing delay per DRAM burst
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system.physmem.avgBankLat 17374.36 # Average bank access latency per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 32058.72 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 2575.37 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 2575.37 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 20.12 # Data bus utilization in percentage
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system.physmem.busUtilRead 20.12 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 758 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 77.74 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 24698.46 # Average gap between requests
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system.physmem.pageHitRate 77.74 # Row buffer hit rate, read and write combined
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system.physmem.prechargeAllPercent 0.09 # Percentage of time for which DRAM has all the banks in precharge state
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system.membus.throughput 2575372996 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 829 # Transaction distribution
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system.membus.trans_dist::ReadResp 829 # Transaction distribution
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system.membus.trans_dist::ReadExReq 146 # Transaction distribution
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system.membus.trans_dist::ReadExResp 146 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 62400 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 1237000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 5.1 # Layer utilization (%)
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system.membus.respLayer1.occupancy 9059500 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 37.4 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.branchPred.lookups 6676 # Number of BP lookups
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system.cpu.branchPred.condPredicted 3772 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 1441 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 4747 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 873 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 18.390562 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 886 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 179 # Number of incorrect RAS predictions.
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 4587 # DTB read hits
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system.cpu.dtb.read_misses 111 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 4698 # DTB read accesses
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system.cpu.dtb.write_hits 2013 # DTB write hits
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system.cpu.dtb.write_misses 86 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 2099 # DTB write accesses
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system.cpu.dtb.data_hits 6600 # DTB hits
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system.cpu.dtb.data_misses 197 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 6797 # DTB accesses
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system.cpu.itb.fetch_hits 5374 # ITB hits
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system.cpu.itb.fetch_misses 57 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 5431 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload0.num_syscalls 17 # Number of system calls
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system.cpu.workload1.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 48460 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 1592 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 37128 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 6676 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 1759 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 6222 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 1834 # Number of cycles fetch has spent squashing
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system.cpu.fetch.MiscStallCycles 325 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.CacheLines 5374 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 890 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 29555 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.256234 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.686456 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 23333 78.95% 78.95% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 540 1.83% 80.77% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 380 1.29% 82.06% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 444 1.50% 83.56% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 426 1.44% 85.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 410 1.39% 86.39% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 457 1.55% 87.94% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 520 1.76% 89.70% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 3045 10.30% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 29555 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.137763 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.766158 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 40476 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 9889 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 5340 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 489 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 2737 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 565 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 333 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 32705 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 703 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 2737 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 41177 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 6164 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 1585 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 5023 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 2245 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 30189 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 54 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.LSQFullEvents 2292 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 22672 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 37159 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 37141 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 13532 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 49 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 6114 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 2970 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 1346 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
|
system.cpu.memDep1.insertedLoads 3034 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep1.insertedStores 1382 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep1.conflictingLoads 1 # Number of conflicting loads.
|
|
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 26322 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 21626 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 131 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 12553 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 8051 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 29555 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.731721 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.328495 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 20216 68.40% 68.40% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 3350 11.33% 79.74% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 2622 8.87% 88.61% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 1591 5.38% 93.99% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 1010 3.42% 97.41% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 474 1.60% 99.01% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 217 0.73% 99.75% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 53 0.18% 99.93% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 22 0.07% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 29555 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 9 4.86% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.86% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 107 57.84% 62.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 69 37.30% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 7076 65.52% 65.54% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.55% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 2585 23.94% 89.50% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 1134 10.50% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 10800 # Type of FU issued
|
|
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IntAlu 7138 65.93% 65.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.96% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::MemRead 2586 23.89% 89.87% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::MemWrite 1097 10.13% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_1::total 10826 # Type of FU issued
|
|
system.cpu.iq.FU_type::total 21626 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.rate 0.446265 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt::0 88 # FU busy when requested
|
|
system.cpu.iq.fu_busy_cnt::1 97 # FU busy when requested
|
|
system.cpu.iq.fu_busy_cnt::total 185 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate::0 0.004069 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.fu_busy_rate::1 0.004485 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.fu_busy_rate::total 0.008555 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 73081 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 38962 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 18684 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 21785 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1787 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 481 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 350 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread1.forwLoads 47 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread1.squashedLoads 1851 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread1.squashedStores 517 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread1.cacheBlocked 407 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 2737 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 2954 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 26599 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 599 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 6004 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 2728 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 78 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 23 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 236 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1303 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 20163 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts::0 2351 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts::1 2365 # Number of load instructions executed
|
|
system.cpu.iew.iewExecLoadInsts::total 4716 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1463 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
|
|
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
|
|
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop::0 109 # number of nop insts executed
|
|
system.cpu.iew.exec_nop::1 90 # number of nop insts executed
|
|
system.cpu.iew.exec_nop::total 199 # number of nop insts executed
|
|
system.cpu.iew.exec_refs::0 3417 # number of memory reference insts executed
|
|
system.cpu.iew.exec_refs::1 3412 # number of memory reference insts executed
|
|
system.cpu.iew.exec_refs::total 6829 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches::0 1584 # Number of branches executed
|
|
system.cpu.iew.exec_branches::1 1595 # Number of branches executed
|
|
system.cpu.iew.exec_branches::total 3179 # Number of branches executed
|
|
system.cpu.iew.exec_stores::0 1066 # Number of stores executed
|
|
system.cpu.iew.exec_stores::1 1047 # Number of stores executed
|
|
system.cpu.iew.exec_stores::total 2113 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.416075 # Inst execution rate
|
|
system.cpu.iew.wb_sent::0 9509 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_sent::1 9507 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_sent::total 19016 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count::0 9333 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_count::1 9371 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_count::total 18704 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers::0 4798 # num instructions producing a value
|
|
system.cpu.iew.wb_producers::1 4830 # num instructions producing a value
|
|
system.cpu.iew.wb_producers::total 9628 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers::0 6247 # num instructions consuming a value
|
|
system.cpu.iew.wb_consumers::1 6320 # num instructions consuming a value
|
|
system.cpu.iew.wb_consumers::total 12567 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate::0 0.192592 # insts written-back per cycle
|
|
system.cpu.iew.wb_rate::1 0.193376 # insts written-back per cycle
|
|
system.cpu.iew.wb_rate::total 0.385968 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout::0 0.768049 # average fanout of values written-back
|
|
system.cpu.iew.wb_fanout::1 0.764241 # average fanout of values written-back
|
|
system.cpu.iew.wb_fanout::total 0.766134 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 13828 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 1125 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 29488 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.433363 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.196034 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 23747 80.53% 80.53% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 3040 10.31% 90.84% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 1123 3.81% 94.65% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 504 1.71% 96.36% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 341 1.16% 97.51% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 269 0.91% 98.43% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 187 0.63% 99.06% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 66 0.22% 99.28% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 211 0.72% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 29488 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts::0 6390 # Number of instructions committed
|
|
system.cpu.commit.committedInsts::1 6389 # Number of instructions committed
|
|
system.cpu.commit.committedInsts::total 12779 # Number of instructions committed
|
|
system.cpu.commit.committedOps::0 6390 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.committedOps::1 6389 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.committedOps::total 12779 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs::0 2048 # Number of memory references committed
|
|
system.cpu.commit.refs::1 2048 # Number of memory references committed
|
|
system.cpu.commit.refs::total 4096 # Number of memory references committed
|
|
system.cpu.commit.loads::0 1183 # Number of loads committed
|
|
system.cpu.commit.loads::1 1183 # Number of loads committed
|
|
system.cpu.commit.loads::total 2366 # Number of loads committed
|
|
system.cpu.commit.membars::0 0 # Number of memory barriers committed
|
|
system.cpu.commit.membars::1 0 # Number of memory barriers committed
|
|
system.cpu.commit.membars::total 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches::0 1050 # Number of branches committed
|
|
system.cpu.commit.branches::1 1050 # Number of branches committed
|
|
system.cpu.commit.branches::total 2100 # Number of branches committed
|
|
system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
|
|
system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
|
|
system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions.
|
|
system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions.
|
|
system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
|
|
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
|
|
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 211 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
|
|
system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
|
|
system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 132697 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 55969 # The number of ROB writes
|
|
system.cpu.timesIdled 379 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 18905 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts::0 6373 # Number of Instructions Simulated
|
|
system.cpu.committedInsts::1 6372 # Number of Instructions Simulated
|
|
system.cpu.committedOps::0 6373 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 12745 # Number of Instructions Simulated
|
|
system.cpu.cpi::0 7.603954 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi::1 7.605148 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 3.802275 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc::0 0.131511 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc::1 0.131490 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.263000 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 25289 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 14129 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 2580655812 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 831 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 831 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 1954 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40064 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 62528 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 488500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1029500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 562500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements::0 6 # number of replacements
|
|
system.cpu.icache.tags.replacements::1 0 # number of replacements
|
|
system.cpu.icache.tags.replacements::total 6 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 312.493120 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 4320 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 626 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 6.900958 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 312.493120 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.152585 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.152585 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 620 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 263 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.302734 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 11364 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 11364 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 4320 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 4320 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 4320 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 4320 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 4320 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 4320 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1049 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1049 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1049 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 69934495 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 69934495 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 69934495 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 69934495 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 69934495 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 69934495 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 5369 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 5369 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 5369 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 5369 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 5369 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 5369 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195381 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.195381 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.195381 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.195381 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.195381 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.195381 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66667.774071 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 66667.774071 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 66667.774071 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 66667.774071 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 66667.774071 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 66667.774071 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 2561 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 44.155172 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 423 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 423 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 423 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 423 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 423 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 423 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 626 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 626 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 626 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 626 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46953746 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 46953746 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46953746 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 46953746 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46953746 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 46953746 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116595 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116595 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116595 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.116595 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116595 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.116595 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75005.984026 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75005.984026 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75005.984026 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 75005.984026 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75005.984026 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 75005.984026 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements::0 0 # number of replacements
|
|
system.cpu.l2cache.tags.replacements::1 0 # number of replacements
|
|
system.cpu.l2cache.tags.replacements::total 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 433.166095 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 829 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.002413 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 313.001767 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 120.164328 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009552 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.003667 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.013219 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 829 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 337 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 492 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025299 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 8791 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 8791 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 624 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 205 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 829 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 624 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 351 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 975 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 624 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 351 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 975 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46304000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16910000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 63214000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11874500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 11874500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 46304000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 28784500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 75088500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 46304000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 28784500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 75088500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 626 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 205 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 831 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 626 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 351 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 977 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 626 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 351 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 977 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.997593 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.997953 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.997953 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74205.128205 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82487.804878 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76253.317250 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81332.191781 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81332.191781 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74205.128205 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82007.122507 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 77013.846154 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74205.128205 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82007.122507 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 77013.846154 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 829 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 975 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38522500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14387500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52910000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10067500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10067500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38522500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24455000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 62977500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38522500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24455000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 62977500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997593 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61734.775641 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70182.926829 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63823.884198 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68955.479452 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68955.479452 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61734.775641 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69672.364672 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64592.307692 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61734.775641 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69672.364672 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64592.307692 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements::0 0 # number of replacements
|
|
system.cpu.dcache.tags.replacements::1 0 # number of replacements
|
|
system.cpu.dcache.tags.replacements::total 0 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 214.018929 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 4470 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 351 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 12.735043 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 214.018929 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.052251 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.052251 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.085693 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 11365 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 11365 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 3448 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 3448 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 4470 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 4470 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 4470 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 4470 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 329 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 329 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1037 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1037 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1037 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1037 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 23849750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 23849750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 50904202 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 50904202 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 74753952 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 74753952 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 74753952 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 74753952 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 3777 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 3777 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 5507 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 5507 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 5507 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 5507 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087106 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.087106 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.188306 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.188306 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.188306 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.188306 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72491.641337 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 72491.641337 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71898.590395 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 71898.590395 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72086.742527 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 72086.742527 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72086.742527 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 72086.742527 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 4541 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 118 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.483051 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 124 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 124 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 686 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 686 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 686 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 686 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 205 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 205 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 351 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 351 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17123000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12022996 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12022996 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29145996 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 29145996 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29145996 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 29145996 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054276 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054276 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063737 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.063737 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063737 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.063737 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83526.829268 # average ReadReq mshr miss latency
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|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83526.829268 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82349.287671 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82349.287671 # average WriteReq mshr miss latency
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|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83037.025641 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 83037.025641 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83037.025641 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 83037.025641 # average overall mshr miss latency
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|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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|
|
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---------- End Simulation Statistics ----------
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