843 lines
96 KiB
Plaintext
843 lines
96 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000020 # Number of seconds simulated
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sim_ticks 19970500 # Number of ticks simulated
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final_tick 19970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 4162 # Simulator instruction rate (inst/s)
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host_op_rate 7540 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 15448311 # Simulator tick rate (ticks/s)
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host_mem_usage 248568 # Number of bytes of host memory used
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host_seconds 1.29 # Real time elapsed on the host
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sim_insts 5380 # Number of instructions simulated
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sim_ops 9747 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
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system.physmem.bytes_read::total 26496 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 414 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 874890463 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 451866503 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1326756967 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 874890463 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 874890463 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 874890463 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 451866503 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1326756967 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 415 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 415 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 26560 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 26560 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 33 # Per bank write bursts
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system.physmem.perBankRdBursts::1 1 # Per bank write bursts
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system.physmem.perBankRdBursts::2 5 # Per bank write bursts
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system.physmem.perBankRdBursts::3 8 # Per bank write bursts
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system.physmem.perBankRdBursts::4 50 # Per bank write bursts
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system.physmem.perBankRdBursts::5 44 # Per bank write bursts
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system.physmem.perBankRdBursts::6 20 # Per bank write bursts
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system.physmem.perBankRdBursts::7 36 # Per bank write bursts
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system.physmem.perBankRdBursts::8 23 # Per bank write bursts
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system.physmem.perBankRdBursts::9 73 # Per bank write bursts
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system.physmem.perBankRdBursts::10 63 # Per bank write bursts
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system.physmem.perBankRdBursts::11 17 # Per bank write bursts
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system.physmem.perBankRdBursts::12 2 # Per bank write bursts
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system.physmem.perBankRdBursts::13 17 # Per bank write bursts
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system.physmem.perBankRdBursts::14 6 # Per bank write bursts
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system.physmem.perBankRdBursts::15 17 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 19922000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 415 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 250 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 226.174757 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 137.685606 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 319.474459 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64 47 45.63% 45.63% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128 17 16.50% 62.14% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192 14 13.59% 75.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256 5 4.85% 80.58% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320 5 4.85% 85.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384 3 2.91% 88.35% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640 4 3.88% 92.23% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704 2 1.94% 94.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896 1 0.97% 95.15% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::960 2 1.94% 97.09% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024 1 0.97% 98.06% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1216 1 0.97% 99.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation
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system.physmem.totQLat 2039250 # Total ticks spent queuing
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system.physmem.totMemAccLat 11731750 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 2075000 # Total ticks spent in databus transfers
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system.physmem.totBankLat 7617500 # Total ticks spent accessing banks
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system.physmem.avgQLat 4913.86 # Average queueing delay per DRAM burst
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system.physmem.avgBankLat 18355.42 # Average bank access latency per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 28269.28 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 1329.96 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 1329.96 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 10.39 # Data bus utilization in percentage
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system.physmem.busUtilRead 10.39 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 0.59 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 312 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 75.18 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 48004.82 # Average gap between requests
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system.physmem.pageHitRate 75.18 # Row buffer hit rate, read and write combined
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system.physmem.prechargeAllPercent 0.06 # Percentage of time for which DRAM has all the banks in precharge state
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system.membus.throughput 1326756967 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 338 # Transaction distribution
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system.membus.trans_dist::ReadResp 337 # Transaction distribution
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system.membus.trans_dist::ReadExReq 77 # Transaction distribution
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system.membus.trans_dist::ReadExResp 77 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 829 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::total 829 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 829 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26496 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26496 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 26496 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 26496 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 500500 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 2.5 # Layer utilization (%)
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system.membus.respLayer1.occupancy 3871500 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 19.4 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.branchPred.lookups 3084 # Number of BP lookups
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system.cpu.branchPred.condPredicted 3084 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 542 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 2283 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 726 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 31.800263 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions.
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system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
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system.cpu.workload.num_syscalls 11 # Number of system calls
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system.cpu.numCycles 39942 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.fetch.icacheStallCycles 10287 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 14134 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 3084 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 3940 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 5300 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 58 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 392 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 1980 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 21845 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.153353 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.669079 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 18006 82.43% 82.43% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 216 0.99% 83.41% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 142 0.65% 84.07% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 224 1.03% 85.09% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 181 0.83% 85.92% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 200 0.92% 86.83% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 275 1.26% 88.09% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 159 0.73% 88.82% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 2442 11.18% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 21845 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.077212 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.353863 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 11079 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 5195 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 3583 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing
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system.cpu.decode.DecodedInsts 24173 # Number of instructions handled by decode
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system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 11444 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 3834 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 603 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 3331 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 776 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 22661 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 663 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 25256 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 55040 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 31380 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 14193 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 30 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 2047 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 2285 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 1565 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 20236 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 17027 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 9729 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 13960 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 21845 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.779446 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.654421 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 16359 74.89% 74.89% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 1539 7.05% 81.93% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 1092 5.00% 86.93% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 724 3.31% 90.24% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 698 3.20% 93.44% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 576 2.64% 96.08% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 581 2.66% 98.74% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 234 1.07% 99.81% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 42 0.19% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 21845 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 140 77.35% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.35% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 26 14.36% 91.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 13667 80.27% 80.28% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.31% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.35% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 1973 11.59% 91.94% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 1373 8.06% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 17027 # Type of FU issued
|
|
system.cpu.iq.rate 0.426293 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 181 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.010630 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 56362 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 29998 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 15642 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 17201 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 168 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1232 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 630 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 3034 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 20262 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 39 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 2285 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 1565 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 686 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 16124 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 1854 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 903 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 0 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 3127 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 1623 # Number of branches executed
|
|
system.cpu.iew.exec_stores 1273 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.403685 # Inst execution rate
|
|
system.cpu.iew.wb_sent 15865 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 15646 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 10128 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 15579 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.391718 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.650106 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 10526 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 19988 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.487643 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.344274 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 16420 82.15% 82.15% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 1360 6.80% 88.95% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 589 2.95% 91.90% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 713 3.57% 95.47% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 364 1.82% 97.29% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 136 0.68% 97.97% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 120 0.60% 98.57% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 74 0.37% 98.94% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 212 1.06% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 19988 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 5380 # Number of instructions committed
|
|
system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 1988 # Number of memory references committed
|
|
system.cpu.commit.loads 1053 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 1208 # Number of branches committed
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 9653 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 106 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 212 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 40049 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 42426 # The number of ROB writes
|
|
system.cpu.timesIdled 166 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 18097 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 5380 # Number of Instructions Simulated
|
|
system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
|
|
system.cpu.cpi 7.424164 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 7.424164 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.134695 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.134695 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 20727 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 12358 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
|
|
system.cpu.cc_regfile_reads 8004 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 4850 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 7135 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 1333166420 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 548 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 833 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 26624 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 208500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 458500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 236000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 0 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 130.946729 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 274 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 5.872263 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 130.946729 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.063939 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.063939 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 274 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 4234 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 4234 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 1609 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 1609 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 1609 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 371 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 25087750 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 25087750 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 25087750 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 25087750 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 25087750 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 25087750 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 1980 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 1980 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 1980 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 1980 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 1980 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187374 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.187374 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.187374 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.187374 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.187374 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.187374 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67621.967655 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 67621.967655 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 67621.967655 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 67621.967655 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 67621.967655 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 67621.967655 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 97 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 97 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 97 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 97 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 97 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 274 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 274 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 274 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 274 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 274 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19639000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 19639000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19639000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 19639000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19639000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 19639000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138384 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.138384 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138384 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.138384 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71675.182482 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71675.182482 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71675.182482 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 71675.182482 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71675.182482 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 71675.182482 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 163.766589 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 337 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.005935 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.016356 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 32.750233 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003998 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.000999 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.004998 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010284 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 3750 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 3750 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 273 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 65 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 338 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 77 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 77 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 273 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 415 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 415 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19353500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5004000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 24357500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5417000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 5417000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 19353500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 10421000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 29774500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 19353500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 10421000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 29774500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 274 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 66 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 77 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 77 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 274 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 417 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 274 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 417 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996350 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.984848 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.994118 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996350 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.993007 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.995204 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996350 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.993007 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.995204 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70891.941392 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76984.615385 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 72063.609467 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70350.649351 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70350.649351 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70891.941392 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73387.323944 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 71745.783133 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70891.941392 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73387.323944 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 71745.783133 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 77 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 77 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 415 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 415 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15927500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4205500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20133000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4457500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4457500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15927500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8663000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 24590500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15927500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8663000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 24590500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.984848 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994118 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995204 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996350 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993007 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995204 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58342.490842 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64700 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59565.088757 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57889.610390 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57889.610390 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58342.490842 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61007.042254 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59254.216867 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58342.490842 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61007.042254 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59254.216867 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 83.239431 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 2337 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 16.457746 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 83.239431 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.020322 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.020322 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 5234 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 5234 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1479 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1479 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 2337 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 2337 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 2337 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 2337 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 132 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 77 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 77 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 209 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 209 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 209 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 209 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 9408000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 9408000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5676000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 5676000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 15084000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 15084000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 15084000 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 15084000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1611 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1611 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2546 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2546 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2546 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2546 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081937 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.081937 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.082353 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.082353 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.082090 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.082090 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.082090 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.082090 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71272.727273 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 71272.727273 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73714.285714 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 73714.285714 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 72172.248804 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 72172.248804 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 72172.248804 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 72172.248804 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 183 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.750000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 66 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 66 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 66 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 77 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5079000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5079000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5494000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5494000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10573000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 10573000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10573000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 10573000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040968 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040968 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.056167 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056167 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.056167 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76954.545455 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76954.545455 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71350.649351 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71350.649351 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73937.062937 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73937.062937 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73937.062937 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73937.062937 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|