234 lines
26 KiB
Text
234 lines
26 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 23807 # Simulator instruction rate (inst/s)
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host_mem_usage 194964 # Number of bytes of host memory used
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host_seconds 0.46 # Real time elapsed on the host
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host_tick_rate 54716973 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 10976 # Number of instructions simulated
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sim_seconds 0.000025 # Number of seconds simulated
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sim_ticks 25237000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 1462 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 1408 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 1458000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.036936 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 1296000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.036936 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
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system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
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system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
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system.cpu.dcache.WriteReq_accesses 1292 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 1187 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 2835000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.081269 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 105 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 2520000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.081269 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 105 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 18.436620 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 2754 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 2595 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 4293000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.057734 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 159 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 3816000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.057734 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 159 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 2754 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 2595 # number of overall hits
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system.cpu.dcache.overall_miss_latency 4293000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.057734 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 159 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 3816000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.057734 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 159 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 99.913779 # Cycle average of tags in use
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system.cpu.dcache.total_refs 2618 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.icache.ReadReq_accesses 11012 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 26908.127208 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 23908.127208 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 10729 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 7615000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.025699 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 283 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 6766000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.025699 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 283 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 37.911661 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 11012 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 26908.127208 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 23908.127208 # average overall mshr miss latency
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system.cpu.icache.demand_hits 10729 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 7615000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.025699 # miss rate for demand accesses
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system.cpu.icache.demand_misses 283 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 6766000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.025699 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 283 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 11012 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 26908.127208 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 23908.127208 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 10729 # number of overall hits
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system.cpu.icache.overall_miss_latency 7615000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.025699 # miss rate for overall accesses
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system.cpu.icache.overall_misses 283 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 6766000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.025699 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 283 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.sampled_refs 283 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 154.924957 # Cycle average of tags in use
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system.cpu.icache.total_refs 10729 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.l2cache.ReadExReq_accesses 88 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 2024000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 88 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 968000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 88 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 337 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 7705000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.994065 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 335 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 3685000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994065 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 335 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 391000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 187000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 0.006289 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 425 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 9729000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.995294 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 4653000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.995294 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 425 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 2 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 9729000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.995294 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 423 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 4653000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.995294 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
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system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
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system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified
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system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued
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system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.sampled_refs 318 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 176.975795 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 0 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 50474 # number of cpu cycles simulated
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system.cpu.num_insts 10976 # Number of instructions executed
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system.cpu.num_refs 2770 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
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---------- End Simulation Statistics ----------
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