8909843a76
This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
1438 lines
170 KiB
Text
1438 lines
170 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 2.903548 # Number of seconds simulated
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sim_ticks 2903547931500 # Number of ticks simulated
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final_tick 2903547931500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 732027 # Simulator instruction rate (inst/s)
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host_op_rate 882601 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 18897780106 # Simulator tick rate (ticks/s)
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host_mem_usage 614620 # Number of bytes of host memory used
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host_seconds 153.65 # Real time elapsed on the host
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sim_insts 112472279 # Number of instructions simulated
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sim_ops 135607130 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.inst 1191972 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9040292 # Number of bytes read from this memory
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system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 10233800 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 1191972 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 1191972 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7641920 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7659444 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.inst 27078 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 141774 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 168876 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 119405 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 123786 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.inst 410523 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3113533 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 3524584 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 410523 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 410523 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 2631925 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 6035 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 2637960 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 2631925 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 410523 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 3119568 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6162545 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 168876 # Number of read requests accepted
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system.physmem.writeReqs 160010 # Number of write requests accepted
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system.physmem.readBursts 168876 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 160010 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 10798592 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue
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system.physmem.bytesWritten 8731520 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 10233800 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 9977780 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 23557 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 4508 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 10030 # Per bank write bursts
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system.physmem.perBankRdBursts::1 9665 # Per bank write bursts
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system.physmem.perBankRdBursts::2 10302 # Per bank write bursts
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system.physmem.perBankRdBursts::3 9920 # Per bank write bursts
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system.physmem.perBankRdBursts::4 18863 # Per bank write bursts
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system.physmem.perBankRdBursts::5 10093 # Per bank write bursts
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system.physmem.perBankRdBursts::6 10296 # Per bank write bursts
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system.physmem.perBankRdBursts::7 10601 # Per bank write bursts
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system.physmem.perBankRdBursts::8 9928 # Per bank write bursts
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system.physmem.perBankRdBursts::9 10198 # Per bank write bursts
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system.physmem.perBankRdBursts::10 9956 # Per bank write bursts
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system.physmem.perBankRdBursts::11 9036 # Per bank write bursts
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system.physmem.perBankRdBursts::12 9857 # Per bank write bursts
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system.physmem.perBankRdBursts::13 10481 # Per bank write bursts
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system.physmem.perBankRdBursts::14 9974 # Per bank write bursts
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system.physmem.perBankRdBursts::15 9528 # Per bank write bursts
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system.physmem.perBankWrBursts::0 8313 # Per bank write bursts
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system.physmem.perBankWrBursts::1 8253 # Per bank write bursts
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system.physmem.perBankWrBursts::2 9067 # Per bank write bursts
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system.physmem.perBankWrBursts::3 8494 # Per bank write bursts
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system.physmem.perBankWrBursts::4 8419 # Per bank write bursts
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system.physmem.perBankWrBursts::5 8394 # Per bank write bursts
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system.physmem.perBankWrBursts::6 8676 # Per bank write bursts
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system.physmem.perBankWrBursts::7 8975 # Per bank write bursts
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system.physmem.perBankWrBursts::8 8824 # Per bank write bursts
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system.physmem.perBankWrBursts::9 8984 # Per bank write bursts
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system.physmem.perBankWrBursts::10 8586 # Per bank write bursts
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system.physmem.perBankWrBursts::11 8136 # Per bank write bursts
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system.physmem.perBankWrBursts::12 8548 # Per bank write bursts
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system.physmem.perBankWrBursts::13 8715 # Per bank write bursts
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system.physmem.perBankWrBursts::14 8203 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7843 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 46 # Number of times write queue was full causing retry
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system.physmem.totGap 2903547607000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 9558 # Read request sizes (log2)
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system.physmem.readPktSize::3 14 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 159304 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 4381 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 155629 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 167922 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 552 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 242 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 1595 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 1890 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 5390 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 5752 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5631 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 5694 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 5724 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 6143 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 7234 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 5981 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 6694 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 7843 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 6228 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 6318 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 8094 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 6968 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 6571 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 6360 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 1258 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 1176 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 1202 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 2331 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 2401 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 1806 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 1887 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 2576 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 1933 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 1944 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 1580 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 1707 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 1648 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 1319 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 1310 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 998 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 760 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 385 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 309 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 230 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 274 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 170 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 161 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 163 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 128 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 123 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 112 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 130 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 64 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 63 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 60277 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 324.004977 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 188.393020 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 342.651376 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 21725 36.04% 36.04% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 14933 24.77% 60.82% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 5631 9.34% 70.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 3281 5.44% 75.60% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2561 4.25% 79.85% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1497 2.48% 82.33% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1055 1.75% 84.08% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1109 1.84% 85.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 8485 14.08% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 60277 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5494 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 30.709319 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 577.316613 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-2047 5492 99.96% 99.96% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 5494 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 5494 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 24.832545 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 18.556239 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 46.623010 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16-31 5170 94.10% 94.10% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::32-47 87 1.58% 95.69% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::48-63 17 0.31% 96.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-79 12 0.22% 96.21% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-95 19 0.35% 96.56% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-111 28 0.51% 97.07% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-127 22 0.40% 97.47% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-143 14 0.25% 97.72% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-159 9 0.16% 97.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::160-175 4 0.07% 97.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::176-191 29 0.53% 98.49% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::192-207 12 0.22% 98.71% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::208-223 6 0.11% 98.82% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-239 2 0.04% 98.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::240-255 2 0.04% 98.89% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::256-271 1 0.02% 98.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::272-287 2 0.04% 98.94% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::288-303 7 0.13% 99.07% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::304-319 8 0.15% 99.22% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::320-335 4 0.07% 99.29% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::336-351 4 0.07% 99.36% # Writes before turning the bus around for reads
|
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system.physmem.wrPerTurnAround::352-367 10 0.18% 99.54% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::368-383 2 0.04% 99.58% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::384-399 3 0.05% 99.64% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::400-415 1 0.02% 99.65% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::416-431 1 0.02% 99.67% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::480-495 4 0.07% 99.75% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::512-527 3 0.05% 99.80% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::528-543 2 0.04% 99.84% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::544-559 6 0.11% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::576-591 1 0.02% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::720-735 1 0.02% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::736-751 1 0.02% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5494 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 1499821694 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 4663471694 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 843640000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 8888.99 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 27638.99 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 3.01 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 3.44 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.05 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 23.13 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 138826 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 106054 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 77.72 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 8828431.76 # Average gap between requests
|
|
system.physmem.pageHitRate 80.24 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 233551080 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 127433625 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 700206000 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 444469680 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 189645583920 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 87280455420 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 1665566622000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 1943998321725 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 669.525264 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 2770655896974 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 96955820000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 35935671776 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 222143040 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 121209000 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 615864600 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 439596720 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 189645583920 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 85782200445 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 1666880880750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 1943707478475 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 669.425095 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 2772857314224 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 96955820000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 33734699276 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 9545 # Table walker walks requested
|
|
system.cpu.dtb.walker.walksShort 9545 # Table walker walks initiated with short descriptors
|
|
system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1267 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8278 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu.dtb.walker.walkWaitTime::samples 9545 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::0 9545 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkWaitTime::total 9545 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::samples 7381 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::mean 10696.619699 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::gmean 8418.408390 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::stdev 7914.312600 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::0-32767 7376 99.93% 99.93% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::32768-65535 1 0.01% 99.95% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walkCompletionTime::total 7381 # Table walker service (enqueue to completion) latency
|
|
system.cpu.dtb.walker.walksPending::samples 937449500 # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walksPending::0 937449500 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walksPending::total 937449500 # Table walker pending requests distribution
|
|
system.cpu.dtb.walker.walkPageSizes::4K 6161 83.47% 83.47% # Table walker page sizes translated
|
|
system.cpu.dtb.walker.walkPageSizes::1M 1220 16.53% 100.00% # Table walker page sizes translated
|
|
system.cpu.dtb.walker.walkPageSizes::total 7381 # Table walker page sizes translated
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9545 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9545 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7381 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7381 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 16926 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 24524755 # DTB read hits
|
|
system.cpu.dtb.read_misses 8132 # DTB read misses
|
|
system.cpu.dtb.write_hits 19610055 # DTB write hits
|
|
system.cpu.dtb.write_misses 1413 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 1678 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 24532887 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 19611468 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 44134810 # DTB hits
|
|
system.cpu.dtb.misses 9545 # DTB misses
|
|
system.cpu.dtb.accesses 44144355 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 4762 # Table walker walks requested
|
|
system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
|
|
system.cpu.itb.walker.walksShortTerminationLevel::Level1 309 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu.itb.walker.walksShortTerminationLevel::Level2 4453 # Level at which table walker walks with short descriptors terminate
|
|
system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::mean 10683.778565 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::gmean 8326.699765 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::stdev 7409.739384 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::0-8191 1442 46.41% 46.41% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::8192-16383 985 31.70% 78.11% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::16384-24575 678 21.82% 99.94% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency
|
|
system.cpu.itb.walker.walksPending::samples 937122000 # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walksPending::0 937122000 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walksPending::total 937122000 # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 115569545 # ITB inst hits
|
|
system.cpu.itb.inst_misses 4762 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 115574307 # ITB inst accesses
|
|
system.cpu.itb.hits 115569545 # DTB hits
|
|
system.cpu.itb.misses 4762 # DTB misses
|
|
system.cpu.itb.accesses 115574307 # DTB accesses
|
|
system.cpu.numCycles 5807095863 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 112472279 # Number of instructions committed
|
|
system.cpu.committedOps 135607130 # Number of ops (including micro ops) committed
|
|
system.cpu.num_int_alu_accesses 119910547 # Number of integer alu accesses
|
|
system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses
|
|
system.cpu.num_func_calls 9892504 # number of times a function call or return occured
|
|
system.cpu.num_conditional_control_insts 15232384 # number of instructions that are conditional controls
|
|
system.cpu.num_int_insts 119910547 # number of integer instructions
|
|
system.cpu.num_fp_insts 11161 # number of float instructions
|
|
system.cpu.num_int_register_reads 218091200 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 82658465 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
|
|
system.cpu.num_cc_register_reads 489812948 # number of times the CC registers were read
|
|
system.cpu.num_cc_register_writes 51900975 # number of times the CC registers were written
|
|
system.cpu.num_mem_refs 45415290 # number of memory refs
|
|
system.cpu.num_load_insts 24846976 # Number of load instructions
|
|
system.cpu.num_store_insts 20568314 # Number of store instructions
|
|
system.cpu.num_idle_cycles 5385642355.670145 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 421453507.329855 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 0.072576 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0.927424 # Percentage of idle cycles
|
|
system.cpu.Branches 25918910 # Number of branches fetched
|
|
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
|
|
system.cpu.op_class::IntAlu 93186875 67.17% 67.17% # Class of executed instruction
|
|
system.cpu.op_class::IntMult 114498 0.08% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMisc 8463 0.01% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction
|
|
system.cpu.op_class::MemRead 24846976 17.91% 85.17% # Class of executed instruction
|
|
system.cpu.op_class::MemWrite 20568314 14.83% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::total 138727463 # Class of executed instruction
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed
|
|
system.cpu.dcache.tags.replacements 820494 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.827736 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 43242693 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 821006 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 52.670374 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 1008712250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.827736 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999664 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 177143306 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 177143306 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 23115915 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 23115915 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 18827300 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 18827300 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 392830 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 392830 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 443506 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 443506 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 460403 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 460403 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 41943215 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 41943215 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 42336045 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 42336045 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 400875 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 400875 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 298693 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 298693 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 118357 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 118357 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22685 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 22685 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 699568 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 699568 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 817925 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 817925 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5965444702 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 5965444702 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 12639649008 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 12639649008 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280760500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 280760500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 18605093710 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 18605093710 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 18605093710 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 18605093710 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 23516790 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 23516790 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 19125993 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 19125993 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 511187 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 511187 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466191 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 466191 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 460405 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 460405 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 42642783 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 42642783 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 43153970 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 43153970 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017046 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.017046 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015617 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231534 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.231534 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048660 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048660 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.016405 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.016405 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.018954 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.018954 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14881.059437 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14881.059437 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42316.522342 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 42316.522342 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12376.482257 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12376.482257 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26595.118287 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 26595.118287 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22746.698915 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 22746.698915 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 683915 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 683915 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 674 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 674 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14143 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 14143 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 674 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 674 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 674 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 674 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400201 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 400201 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298693 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 298693 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116343 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 116343 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8542 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 8542 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 698894 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 698894 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 815237 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 815237 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5349732750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5349732750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12133728492 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 12133728492 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1470377548 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1470377548 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105335000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105335000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17483461242 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 17483461242 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18953838790 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 18953838790 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5833129500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5833129500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4513032000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4513032000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346161500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346161500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017018 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017018 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227594 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227594 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018323 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018323 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016390 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.016390 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018891 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.018891 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13367.614649 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13367.614649 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40622.741383 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40622.741383 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12638.298376 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12638.298376 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12331.421213 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12331.421213 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25015.898322 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25015.898322 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23249.483022 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23249.483022 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 1698619 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 510.734312 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 113870408 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 1699131 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 67.016850 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 25693423250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.734312 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.997528 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.997528 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 117268682 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 117268682 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 113870408 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 113870408 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 113870408 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 113870408 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 113870408 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 113870408 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1699137 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1699137 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1699137 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1699137 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1699137 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1699137 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 23363194999 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 23363194999 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 23363194999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 23363194999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 23363194999 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 23363194999 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 115569545 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 115569545 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 115569545 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 115569545 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 115569545 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 115569545 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014702 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.014702 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.014702 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.014702 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.014702 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.014702 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13750.036047 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 13750.036047 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13750.036047 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 13750.036047 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13750.036047 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 13750.036047 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1699137 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1699137 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1699137 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1699137 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1699137 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1699137 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20807922501 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 20807922501 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20807922501 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 20807922501 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20807922501 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 20807922501 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 677067750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 677067750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 677067750 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency::total 677067750 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014702 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.014702 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.014702 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12246.171145 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12246.171145 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 89783 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 64925.975304 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2753164 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 155016 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 17.760515 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 50459.043234 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.807659 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012269 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9560.730853 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 4902.381289 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.769944 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.145885 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.074804 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.990692 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65228 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6958 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56095 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995300 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 26192754 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 26192754 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6798 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3551 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1681053 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 512833 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2204235 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 683915 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 683915 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 164921 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 164921 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6798 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 3551 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1681053 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 677754 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2369156 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6798 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 3551 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1681053 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 677754 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2369156 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 18063 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 12253 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 30325 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2714 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2714 # number of UpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 131035 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 131035 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 18063 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 143288 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 161360 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 18063 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 143288 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 161360 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 722250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 165500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1457697500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1014855798 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 2473441048 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 528483 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 528483 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10018114706 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 10018114706 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 722250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 165500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1457697500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 11032970504 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 12491555754 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 722250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 165500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1457697500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 11032970504 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 12491555754 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6805 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3553 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699116 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 525086 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2234560 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 683915 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 683915 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2737 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 2737 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 295956 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 295956 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6805 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3553 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1699116 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 821042 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2530516 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6805 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3553 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1699116 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 821042 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2530516 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001029 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010631 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.023335 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.013571 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991597 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991597 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.442752 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.442752 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001029 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010631 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.174520 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.063766 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001029 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010631 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.174520 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.063766 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 103178.571429 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82750 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80700.741848 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82825.087570 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 81564.420379 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 194.724761 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 194.724761 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76453.731492 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76453.731492 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 103178.571429 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82750 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80700.741848 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76998.565853 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 77414.202739 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 103178.571429 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82750 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80700.741848 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76998.565853 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 77414.202739 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 83215 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 83215 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 18063 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 12253 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 30325 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2714 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2714 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131035 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 131035 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 18063 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 143288 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 161360 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 18063 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 143288 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 161360 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 635250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 140500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1231366500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 861613702 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2093755952 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48365714 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48365714 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 135000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8377798294 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8377798294 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 635250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 140500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1231366500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9239411996 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 10471554246 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 635250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 140500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1231366500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9239411996 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 10471554246 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 546237750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5396778750 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5943016500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4154268500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4154268500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 546237750 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9551047250 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10097285000 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023335 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013571 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991597 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991597 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442752 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442752 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.174520 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063766 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.174520 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063766 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70250 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68170.652715 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70318.591529 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69043.889596 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17820.823139 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17820.823139 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63935.576709 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63935.576709 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70250 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70250 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2291655 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2291640 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 683915 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2737 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2739 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 295956 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 295956 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3416297 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2449150 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12768 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24628 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 5902843 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108779512 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96514397 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14212 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27220 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 205335341 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 53413 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 3270364 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 3.011159 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.105044 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 3233871 98.88% 98.88% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 36493 1.12% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 3270364 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 2348519500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 2563126749 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 1308606460 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer3.occupancy 17823250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 59014 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 22790 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 198904691 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 36849506 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 36424 # number of replacements
|
|
system.iocache.tags.tagsinuse 1.079220 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 309085643000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ide 1.079220 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ide 0.067451 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.067451 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 328122 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 328122 # Number of data accesses
|
|
system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 234 # number of ReadReq misses
|
|
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
|
|
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
|
|
system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 234 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ide 234 # number of overall misses
|
|
system.iocache.overall_misses::total 234 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ide 28886876 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 28886876 # number of ReadReq miss cycles
|
|
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6649316309 # number of WriteInvalidateReq miss cycles
|
|
system.iocache.WriteInvalidateReq_miss_latency::total 6649316309 # number of WriteInvalidateReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 28886876 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 28886876 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 28886876 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 28886876 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 123448.188034 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 123448.188034 # average ReadReq miss latency
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183561.073018 # average WriteInvalidateReq miss latency
|
|
system.iocache.WriteInvalidateReq_avg_miss_latency::total 183561.073018 # average WriteInvalidateReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 123448.188034 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 123448.188034 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 123448.188034 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 123448.188034 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 22762 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 6.636152 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
|
system.iocache.writebacks::total 36190 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 16499876 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 16499876 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4765656321 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4765656321 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 16499876 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 16499876 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 16499876 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 16499876 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70512.290598 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 70512.290598 # average ReadReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131560.742077 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131560.742077 # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 70512.290598 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 70512.290598 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70512.290598 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 70512.290598 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 70719 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 70719 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 27589 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 27589 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 119405 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4508 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 4510 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 129241 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 129241 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438994 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546586 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 655473 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15576124 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15739477 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 20374933 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 498 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 319985 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 319985 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 319985 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 90499500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 1700000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 980923653 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 964658040 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 37509494 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
|
|
---------- End Simulation Statistics ----------
|