gem5/tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
Steve Reinhardt 89ea323250 Update stats for new prefetching fixes.
Prefetching is not enabled in any of our regressions, so no significant
stat values have changed, but zero-valued prefetch stats no longer
show up when prefetching is disabled so there are noticable changes
in the reference stat files anyway.
2009-02-16 12:09:45 -05:00

54 lines
4.8 KiB
Text

---------- Begin Simulation Statistics ----------
host_inst_rate 24803 # Simulator instruction rate (inst/s)
host_mem_usage 193824 # Number of bytes of host memory used
host_seconds 0.23 # Real time elapsed on the host
host_tick_rate 12384497 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5656 # Number of instructions simulated
sim_seconds 0.000003 # Number of seconds simulated
sim_ticks 2828000 # Number of ticks simulated
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 5657 # number of cpu cycles simulated
system.cpu.num_insts 5656 # Number of instructions executed
system.cpu.num_refs 2055 # Number of memory references
system.cpu.tlb.accesses 0 # DTB accesses
system.cpu.tlb.accesses 0 # DTB accesses
system.cpu.tlb.hits 0 # DTB hits
system.cpu.tlb.hits 0 # DTB hits
system.cpu.tlb.misses 0 # DTB misses
system.cpu.tlb.misses 0 # DTB misses
system.cpu.tlb.read_accesses 0 # DTB read accesses
system.cpu.tlb.read_accesses 0 # DTB read accesses
system.cpu.tlb.read_hits 0 # DTB read hits
system.cpu.tlb.read_hits 0 # DTB read hits
system.cpu.tlb.read_misses 0 # DTB read misses
system.cpu.tlb.read_misses 0 # DTB read misses
system.cpu.tlb.write_accesses 0 # DTB write accesses
system.cpu.tlb.write_accesses 0 # DTB write accesses
system.cpu.tlb.write_hits 0 # DTB write hits
system.cpu.tlb.write_hits 0 # DTB write hits
system.cpu.tlb.write_misses 0 # DTB write misses
system.cpu.tlb.write_misses 0 # DTB write misses
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
---------- End Simulation Statistics ----------