1276 lines
148 KiB
Text
1276 lines
148 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.235850 # Number of seconds simulated
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sim_ticks 235850129000 # Number of ticks simulated
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final_tick 235850129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 254127 # Simulator instruction rate (inst/s)
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host_op_rate 275309 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 118629630 # Simulator tick rate (ticks/s)
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host_mem_usage 302132 # Number of bytes of host memory used
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host_seconds 1988.12 # Real time elapsed on the host
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sim_insts 505234934 # Number of instructions simulated
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sim_ops 547348155 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::cpu.inst 651264 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 10497792 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.l2cache.prefetcher 16410048 # Number of bytes read from this memory
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system.physmem.bytes_read::total 27559104 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 651264 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 651264 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 18653440 # Number of bytes written to this memory
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system.physmem.bytes_written::total 18653440 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 10176 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 164028 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.l2cache.prefetcher 256407 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 430611 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 291460 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 291460 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 2761347 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 44510436 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.l2cache.prefetcher 69578287 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 116850070 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 2761347 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 2761347 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 79090226 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 79090226 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 79090226 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 2761347 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 44510436 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.l2cache.prefetcher 69578287 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 195940296 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 430611 # Number of read requests accepted
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system.physmem.writeReqs 291460 # Number of write requests accepted
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system.physmem.readBursts 430611 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 291460 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 27396288 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 162816 # Total number of bytes read from write queue
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system.physmem.bytesWritten 18651392 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 27559104 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 18653440 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 2544 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 9 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 27102 # Per bank write bursts
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system.physmem.perBankRdBursts::1 26174 # Per bank write bursts
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system.physmem.perBankRdBursts::2 25664 # Per bank write bursts
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system.physmem.perBankRdBursts::3 33006 # Per bank write bursts
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system.physmem.perBankRdBursts::4 27996 # Per bank write bursts
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system.physmem.perBankRdBursts::5 29984 # Per bank write bursts
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system.physmem.perBankRdBursts::6 25487 # Per bank write bursts
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system.physmem.perBankRdBursts::7 24586 # Per bank write bursts
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system.physmem.perBankRdBursts::8 25526 # Per bank write bursts
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system.physmem.perBankRdBursts::9 25681 # Per bank write bursts
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system.physmem.perBankRdBursts::10 25862 # Per bank write bursts
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system.physmem.perBankRdBursts::11 26092 # Per bank write bursts
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system.physmem.perBankRdBursts::12 27614 # Per bank write bursts
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system.physmem.perBankRdBursts::13 26106 # Per bank write bursts
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system.physmem.perBankRdBursts::14 25123 # Per bank write bursts
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system.physmem.perBankRdBursts::15 26064 # Per bank write bursts
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system.physmem.perBankWrBursts::0 18530 # Per bank write bursts
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system.physmem.perBankWrBursts::1 18172 # Per bank write bursts
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system.physmem.perBankWrBursts::2 17960 # Per bank write bursts
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system.physmem.perBankWrBursts::3 17946 # Per bank write bursts
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system.physmem.perBankWrBursts::4 18535 # Per bank write bursts
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system.physmem.perBankWrBursts::5 18092 # Per bank write bursts
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system.physmem.perBankWrBursts::6 17937 # Per bank write bursts
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system.physmem.perBankWrBursts::7 17864 # Per bank write bursts
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system.physmem.perBankWrBursts::8 17881 # Per bank write bursts
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system.physmem.perBankWrBursts::9 17814 # Per bank write bursts
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system.physmem.perBankWrBursts::10 18253 # Per bank write bursts
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system.physmem.perBankWrBursts::11 18685 # Per bank write bursts
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system.physmem.perBankWrBursts::12 18794 # Per bank write bursts
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system.physmem.perBankWrBursts::13 18180 # Per bank write bursts
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system.physmem.perBankWrBursts::14 18427 # Per bank write bursts
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system.physmem.perBankWrBursts::15 18358 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 235850076500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 430611 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 291460 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 318665 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 60579 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 13349 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 9026 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 7328 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 6151 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 5231 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 4311 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 3288 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 74 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 37 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 14 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 6820 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 7302 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 12035 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 14838 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 16182 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 16933 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 17312 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 17637 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 17893 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 18126 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 18306 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 18426 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 18598 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 18683 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 18906 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 18563 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 17444 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 17201 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 121 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 18 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 16 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 329170 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 139.885214 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 98.537517 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 178.782393 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 210239 63.87% 63.87% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 79533 24.16% 88.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 14816 4.50% 92.53% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 7238 2.20% 94.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 4909 1.49% 96.22% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 2469 0.75% 96.97% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1818 0.55% 97.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1563 0.47% 98.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 6585 2.00% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 329170 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 17054 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 25.096224 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 145.074041 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 17052 99.99% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 17054 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 17054 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 17.088542 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 17.022727 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 1.689258 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16-17 9980 58.52% 58.52% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18-19 6296 36.92% 95.44% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20-21 558 3.27% 98.71% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::22-23 128 0.75% 99.46% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::24-25 50 0.29% 99.75% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::26-27 15 0.09% 99.84% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::28-29 10 0.06% 99.90% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::30-31 6 0.04% 99.94% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::32-33 2 0.01% 99.95% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::34-35 1 0.01% 99.95% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::36-37 1 0.01% 99.96% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::42-43 3 0.02% 99.98% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::46-47 1 0.01% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::62-63 1 0.01% 99.99% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::74-75 2 0.01% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 17054 # Writes before turning the bus around for reads
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system.physmem.totQLat 14249250266 # Total ticks spent queuing
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system.physmem.totMemAccLat 22275506516 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 2140335000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 33287.43 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 52037.43 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 116.16 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 79.08 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 116.85 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 79.09 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 1.53 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing
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system.physmem.readRowHits 308139 # Number of row buffer hits during reads
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system.physmem.writeRowHits 82177 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 71.98 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 28.20 # Row buffer hit rate for writes
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system.physmem.avgGap 326630.04 # Average gap between requests
|
|
system.physmem.pageHitRate 54.25 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 1195207440 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 635245050 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1570792860 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 757087920 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 15735398640.000004 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 13510945980 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 615046560 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.actPowerDownEnergy 46117601610 # Energy for active power-down per rank (pJ)
|
|
system.physmem_0.prePowerDownEnergy 17430135360 # Energy for precharge power-down per rank (pJ)
|
|
system.physmem_0.selfRefreshEnergy 15587831640 # Energy for self refresh per rank (pJ)
|
|
system.physmem_0.totalEnergy 113161874670 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 479.804155 # Core power per rank (mW)
|
|
system.physmem_0.totalIdleTime 204603400415 # Total Idle time Per DRAM Rank
|
|
system.physmem_0.memoryStateTime::IDLE 912794276 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 6674692000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::SREF 58078463500 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 45390268663 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 23659127059 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 101134783502 # Time in different power states
|
|
system.physmem_1.actEnergy 1155130620 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 613955100 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1485605520 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 764166240 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 15039011520.000004 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 13474802850 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 604322400 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.actPowerDownEnergy 42537889890 # Energy for active power-down per rank (pJ)
|
|
system.physmem_1.prePowerDownEnergy 17081497440 # Energy for precharge power-down per rank (pJ)
|
|
system.physmem_1.selfRefreshEnergy 17718944700 # Energy for self refresh per rank (pJ)
|
|
system.physmem_1.totalEnergy 110481339780 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 468.438739 # Core power per rank (mW)
|
|
system.physmem_1.totalIdleTime 204713337667 # Total Idle time Per DRAM Rank
|
|
system.physmem_1.memoryStateTime::IDLE 914400899 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 6380142000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::SREF 66945121250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 44482448304 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 23842248434 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 93285768113 # Time in different power states
|
|
system.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.branchPred.lookups 174426540 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 130958868 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 7258964 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 89936054 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 78903188 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 87.732544 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 12071651 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 104612 # Number of incorrect RAS predictions.
|
|
system.cpu.branchPred.indirectLookups 4685817 # Number of indirect predictor lookups.
|
|
system.cpu.branchPred.indirectHits 4672093 # Number of indirect target hits.
|
|
system.cpu.branchPred.indirectMisses 13724 # Number of indirect misses.
|
|
system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 548 # Number of system calls
|
|
system.cpu.pwrStateResidencyTicks::ON 235850129000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.numCycles 471700259 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 7689412 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 726848478 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 174426540 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 95646932 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 455559849 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 14571167 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 7088 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 169 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 15067 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 235109896 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 36736 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 470557168 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.672087 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.189865 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 101222144 21.51% 21.51% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 131885544 28.03% 49.54% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 57421464 12.20% 61.74% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 180028016 38.26% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 470557168 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.369783 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.540912 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 32637512 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 125886415 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 282414401 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 22855437 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 6763403 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 71909343 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 530427 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 710086582 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 29127059 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 6763403 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 63488458 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 61155779 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 40463668 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 273022741 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 25663119 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 681926435 # Number of instructions processed by rename
|
|
system.cpu.rename.SquashedInsts 12775010 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 10060236 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 2531231 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 1813266 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 2373970 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 826391408 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 2997146717 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 717894841 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 172295734 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 1545774 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 1536126 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 43961162 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 142203026 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 67513624 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 12913434 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 11193544 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 664083030 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 2979301 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 608560988 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 5743597 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 119714176 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 304959820 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1669 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 470557168 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.293277 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.104886 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 154355830 32.80% 32.80% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 100909501 21.44% 54.25% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 145256303 30.87% 85.12% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 63003898 13.39% 98.51% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 7030993 1.49% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 643 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 470557168 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 71776446 52.99% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 30 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 44249945 32.67% 85.65% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 19436717 14.35% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMemRead 9 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMemWrite 22 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 412327933 67.75% 67.75% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 351836 0.06% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 133457436 21.93% 89.74% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 62423748 10.26% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMemRead 16 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMemWrite 16 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 608560988 # Type of FU issued
|
|
system.cpu.iq.rate 1.290143 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 135463169 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.222596 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 1828885813 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 786805257 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 593918713 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 97 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 744024094 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 63 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 7272380 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 26319743 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 24134 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 29234 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 10653404 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 224604 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 23301 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 6763403 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 23756716 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 981361 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 668554311 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 142203026 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 67513624 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1490759 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 256987 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 586437 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 29234 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 3560929 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 3767464 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 7328393 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 598121332 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 128978812 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 10439656 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 1491980 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 189925083 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 131214447 # Number of branches executed
|
|
system.cpu.iew.exec_stores 60946271 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.268011 # Inst execution rate
|
|
system.cpu.iew.wb_sent 595160432 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 593918729 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 349300209 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 571006140 # num instructions consuming a value
|
|
system.cpu.iew.wb_rate 1.259102 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.611728 # average fanout of values written-back
|
|
system.cpu.commit.commitSquashedInsts 106531473 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 6736784 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 453954004 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.208695 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.885174 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 225266208 49.62% 49.62% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 116316093 25.62% 75.25% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 43463338 9.57% 84.82% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 23021553 5.07% 89.89% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 11663985 2.57% 92.46% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 7751412 1.71% 94.17% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 8276330 1.82% 95.99% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 4247049 0.94% 96.93% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 13948036 3.07% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 453954004 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 506578818 # Number of instructions committed
|
|
system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 172743503 # Number of memory references committed
|
|
system.cpu.commit.loads 115883283 # Number of loads committed
|
|
system.cpu.commit.membars 1488542 # Number of memory barriers committed
|
|
system.cpu.commit.branches 121552863 # Number of branches committed
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 448447003 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 375609314 68.46% 68.46% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMisc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 56860204 10.36% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMemWrite 16 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 13948036 # number cycles where commit BW limit reached
|
|
system.cpu.rob.rob_reads 1095222342 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 1327086117 # The number of ROB writes
|
|
system.cpu.timesIdled 14782 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 1143091 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 505234934 # Number of Instructions Simulated
|
|
system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.933626 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.933626 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.071093 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.071093 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 609897818 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 327085541 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.cc_regfile_reads 2165040622 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 376344417 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 217537377 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
|
|
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.tags.replacements 2817480 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.627959 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 168773991 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2817992 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 59.891579 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 504701000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.627959 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 355076080 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 355076080 # Number of data accesses
|
|
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 114071383 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 114071383 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 51722665 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 51722665 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 2778 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 2778 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 1488556 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 165794048 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 165794048 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 165796826 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 165796826 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 4838662 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 4838662 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 2516384 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 2516384 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 10 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 65 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 65 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 7355046 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 7355046 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 7355056 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 7355056 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 63735397500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 63735397500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 19938555937 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 19938555937 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 846000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 846000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 83673953437 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 83673953437 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 83673953437 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 83673953437 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 118910045 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 118910045 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2788 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 2788 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488621 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 1488621 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 173149094 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 173149094 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 173151882 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 173151882 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040692 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.040692 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046394 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.046394 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003587 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.003587 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.042478 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.042478 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.042477 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.042477 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13172.111939 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 13172.111939 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7923.494958 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 7923.494958 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13015.384615 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13015.384615 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 11376.401104 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 11376.401104 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 11376.385637 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 11376.385637 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 14 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 1100252 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 221126 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.666667 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 4.975679 # average number of cycles each access was blocked
|
|
system.cpu.dcache.writebacks::writebacks 2817480 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 2817480 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540507 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 2540507 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996523 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1996523 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 65 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 65 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 4537030 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 4537030 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 4537030 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 4537030 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298155 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 2298155 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519861 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 519861 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 9 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2818016 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2818016 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2818025 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2818025 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32727255000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 32727255000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4791332496 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4791332496 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1174000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1174000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37518587496 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 37518587496 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37519761496 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 37519761496 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019327 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019327 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009585 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009585 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003228 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003228 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016275 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.016275 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016275 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.016275 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14240.664794 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14240.664794 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9216.564612 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9216.564612 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 130444.444444 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 130444.444444 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13313.830545 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 13313.830545 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13314.204628 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13314.204628 # average overall mshr miss latency
|
|
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.tags.replacements 76537 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 465.899675 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 235023805 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 77049 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 3050.316098 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 116553680500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 465.899675 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.909960 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.909960 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 14 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 470296624 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 470296624 # Number of data accesses
|
|
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 235023805 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 235023805 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 235023805 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 235023805 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 235023805 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 235023805 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 85967 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 85967 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 85967 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 85967 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 85967 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 85967 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1954653197 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 1954653197 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 1954653197 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 1954653197 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 1954653197 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 1954653197 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 235109772 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 235109772 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 235109772 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 235109772 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 235109772 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 235109772 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22737.250305 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 22737.250305 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22737.250305 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 22737.250305 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22737.250305 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 22737.250305 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 201943 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 336 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 7203 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 28.035957 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked
|
|
system.cpu.icache.writebacks::writebacks 76537 # number of writebacks
|
|
system.cpu.icache.writebacks::total 76537 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8885 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 8885 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 8885 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 8885 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 8885 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 8885 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77082 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 77082 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 77082 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 77082 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 77082 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 77082 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1551815800 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 1551815800 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1551815800 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 1551815800 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1551815800 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 1551815800 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20132.012662 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20132.012662 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20132.012662 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 20132.012662 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20132.012662 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 20132.012662 # average overall mshr miss latency
|
|
system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 8513754 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.pfIdentified 8515198 # number of prefetch candidates identified
|
|
system.cpu.l2cache.prefetcher.pfBufferHit 454 # number of redundant prefetches already in prefetch queue
|
|
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu.l2cache.prefetcher.pfSpanPage 744250 # number of prefetches not generated due to page crossing
|
|
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.tags.replacements 390446 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 15006.522104 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2698185 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 406039 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 6.645138 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 14933.160754 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 73.361350 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.911448 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004478 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.915925 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1022 107 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15486 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 51 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 675 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5453 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6496 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2623 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006531 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945190 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 95374967 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 95374967 # Number of data accesses
|
|
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.l2cache.WritebackDirty_hits::writebacks 2350430 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackDirty_hits::total 2350430 # number of WritebackDirty hits
|
|
system.cpu.l2cache.WritebackClean_hits::writebacks 520007 # number of WritebackClean hits
|
|
system.cpu.l2cache.WritebackClean_hits::total 520007 # number of WritebackClean hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 516734 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 516734 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 66859 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadCleanReq_hits::total 66859 # number of ReadCleanReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2131098 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.ReadSharedReq_hits::total 2131098 # number of ReadSharedReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 66859 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 2647832 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2714691 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 66859 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 2647832 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2714691 # number of overall hits
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 33 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 33 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 5281 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 5281 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10187 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadCleanReq_misses::total 10187 # number of ReadCleanReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 164879 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.ReadSharedReq_misses::total 164879 # number of ReadSharedReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 10187 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 170160 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 180347 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 10187 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 170160 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 180347 # number of overall misses
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 87000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 87000 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 674041000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 674041000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1035576000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_miss_latency::total 1035576000 # number of ReadCleanReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15320195500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_miss_latency::total 15320195500 # number of ReadSharedReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1035576000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 15994236500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 17029812500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1035576000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 15994236500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 17029812500 # number of overall miss cycles
|
|
system.cpu.l2cache.WritebackDirty_accesses::writebacks 2350430 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackDirty_accesses::total 2350430 # number of WritebackDirty accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::writebacks 520007 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.WritebackClean_accesses::total 520007 # number of WritebackClean accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 33 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 33 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 522015 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 522015 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 77046 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadCleanReq_accesses::total 77046 # number of ReadCleanReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295977 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadSharedReq_accesses::total 2295977 # number of ReadSharedReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 77046 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2817992 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2895038 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 77046 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2817992 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2895038 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.010117 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.010117 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.132220 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.132220 # miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.071812 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.071812 # miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.132220 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.060383 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.062295 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.132220 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.060383 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.062295 # miss rate for overall accesses
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2636.363636 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2636.363636 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127635.106987 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127635.106987 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 101656.621184 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 101656.621184 # average ReadCleanReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92917.809424 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92917.809424 # average ReadSharedReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 101656.621184 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93995.277974 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 94428.033180 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 101656.621184 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93995.277974 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 94428.033180 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 349 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 349 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.unused_prefetches 1991 # number of HardPF blocks evicted w/o reference
|
|
system.cpu.l2cache.writebacks::writebacks 291460 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 291460 # number of writebacks
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1597 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::total 1597 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4534 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4534 # number of ReadSharedReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 6131 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 6142 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 6131 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 6142 # number of overall MSHR hits
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 356126 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::total 356126 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3684 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 3684 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10176 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10176 # number of ReadCleanReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160345 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160345 # number of ReadSharedReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 10176 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 164029 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 174205 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10176 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 164029 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 356126 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 530331 # number of overall MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21400232213 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 517000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 517000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 462922500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 462922500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 973097500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 973097500 # number of ReadCleanReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13944331500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13944331500 # number of ReadSharedReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 973097500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14407254000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 15380351500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 973097500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14407254000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 36780583713 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007057 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007057 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.132077 # mshr miss rate for ReadCleanReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069837 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069837 # mshr miss rate for ReadSharedReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058208 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.060174 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058208 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.183186 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 60091.743408 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15666.666667 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15666.666667 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 125657.573290 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 125657.573290 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95626.719733 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95626.719733 # average ReadCleanReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 86964.554554 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86964.554554 # average ReadSharedReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95626.719733 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87833.578209 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88288.806291 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95626.719733 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87833.578209 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69354.014216 # average overall mshr miss latency
|
|
system.cpu.toL2Bus.snoop_filter.tot_requests 5789124 # Total number of requests made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894045 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26043 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.tot_snoops 99823 # Total number of snoops made to the snoop filter.
|
|
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99226 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 597 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2373057 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackDirty 2641890 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WritebackClean 543587 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::CleanEvict 98986 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFReq 403295 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 33 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 33 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 522015 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 522015 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadCleanReq 77082 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295977 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230663 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453531 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 8684194 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9829184 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360670272 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 370499456 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 793778 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoopTraffic 18655808 # Total snoop traffic (bytes)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 3688848 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 0.034290 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.182859 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 3562956 96.59% 96.59% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 125295 3.40% 99.98% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 597 0.02% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 3688848 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 5788579005 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 115655928 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 4227026456 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%)
|
|
system.membus.snoop_filter.tot_requests 821093 # Total number of requests made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_requests 414041 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
|
|
system.membus.trans_dist::ReadResp 426929 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 291460 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 98986 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 36 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 3681 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 3681 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 426930 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251703 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1251703 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46212480 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 46212480 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
|
|
system.membus.snoop_fanout::samples 430647 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 430647 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 430647 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 2213026745 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2279181090 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|