eddac53ff6
At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
588 lines
20 KiB
C++
588 lines
20 KiB
C++
/*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/mips/isa.hh"
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#include "arch/mips/mt.hh"
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#include "arch/mips/mt_constants.hh"
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#include "arch/mips/pra_constants.hh"
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#include "base/bitfield.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "debug/MipsPRA.hh"
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namespace MipsISA
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{
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std::string
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ISA::miscRegNames[NumMiscRegs] =
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{
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"Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
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"Random", "VPEControl", "VPEConf0", "VPEConf1",
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"YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt",
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"EntryLo0", "TCStatus", "TCBind", "TCRestart",
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"TCHalt", "TCContext", "TCSchedule", "TCScheFBack",
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"EntryLo1", "", "", "", "", "", "", "",
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"Context", "ContextConfig", "", "", "", "", "", "",
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"PageMask", "PageGrain", "", "", "", "", "", "",
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"Wired", "SRSConf0", "SRCConf1", "SRSConf2",
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"SRSConf3", "SRSConf4", "", "",
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"HWREna", "", "", "", "", "", "", "",
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"BadVAddr", "", "", "", "", "", "", "",
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"Count", "", "", "", "", "", "", "",
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"EntryHi", "", "", "", "", "", "", "",
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"Compare", "", "", "", "", "", "", "",
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"Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "",
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"Cause", "", "", "", "", "", "", "",
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"EPC", "", "", "", "", "", "", "",
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"PRId", "EBase", "", "", "", "", "", "",
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"Config", "Config1", "Config2", "Config3", "", "", "", "",
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"LLAddr", "", "", "", "", "", "", "",
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"WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3",
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"WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7",
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"WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3",
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"WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7",
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"XCContext64", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"Debug", "TraceControl1", "TraceControl2", "UserTraceData",
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"TraceBPC", "", "", "",
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"DEPC", "", "", "", "", "", "", "",
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"PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3",
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"PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7",
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"ErrCtl", "", "", "", "", "", "", "",
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"CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "",
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"TagLo0", "DataLo1", "TagLo2", "DataLo3",
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"TagLo4", "DataLo5", "TagLo6", "DataLo7",
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"TagHi0", "DataHi1", "TagHi2", "DataHi3",
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"TagHi4", "DataHi5", "TagHi6", "DataHi7",
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"ErrorEPC", "", "", "", "", "", "", "",
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"DESAVE", "", "", "", "", "", "", "",
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"LLFlag"
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};
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ISA::ISA(uint8_t num_threads, uint8_t num_vpes)
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{
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numThreads = num_threads;
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numVpes = num_vpes;
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miscRegFile.resize(NumMiscRegs);
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bankType.resize(NumMiscRegs);
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for (int i=0; i < NumMiscRegs; i++) {
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miscRegFile[i].resize(1);
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bankType[i] = perProcessor;
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}
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miscRegFile_WriteMask.resize(NumMiscRegs);
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for (int i = 0; i < NumMiscRegs; i++) {
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miscRegFile_WriteMask[i].push_back(0);
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}
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// Initialize all Per-VPE regs
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uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL,
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MISCREG_VPE_CONF0, MISCREG_VPE_CONF1,
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MISCREG_YQMASK,
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MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK,
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MISCREG_VPE_OPT, MISCREG_SRS_CONF0,
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MISCREG_SRS_CONF1, MISCREG_SRS_CONF2,
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MISCREG_SRS_CONF3, MISCREG_SRS_CONF4,
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MISCREG_EBASE
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};
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uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
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for (int i = 0; i < num_vpe_regs; i++) {
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if (numVpes > 1) {
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miscRegFile[per_vpe_regs[i]].resize(numVpes);
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}
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bankType[per_vpe_regs[i]] = perVirtProcessor;
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}
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// Initialize all Per-TC regs
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uint32_t per_tc_regs[] = { MISCREG_STATUS,
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MISCREG_TC_STATUS, MISCREG_TC_BIND,
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MISCREG_TC_RESTART, MISCREG_TC_HALT,
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MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE,
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MISCREG_TC_SCHEFBACK,
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MISCREG_DEBUG, MISCREG_LLADDR
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};
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uint32_t num_tc_regs = sizeof(per_tc_regs) / 4;
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for (int i = 0; i < num_tc_regs; i++) {
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miscRegFile[per_tc_regs[i]].resize(numThreads);
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bankType[per_tc_regs[i]] = perThreadContext;
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}
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clear();
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}
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void
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ISA::clear()
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{
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for(int i = 0; i < NumMiscRegs; i++) {
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for (int j = 0; j < miscRegFile[i].size(); j++)
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miscRegFile[i][j] = 0;
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for (int k = 0; k < miscRegFile_WriteMask[i].size(); k++)
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miscRegFile_WriteMask[i][k] = (long unsigned int)(-1);
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}
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}
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void
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ISA::configCP()
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{
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DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
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numThreads, numVpes);
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CoreSpecific cp;
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panic("CP state must be set before the following code is used");
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// Do Default CP0 initialization HERE
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// Do Initialization for MT cores here (eventually use
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// core_name parameter to toggle this initialization)
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// ===================================================
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DPRINTF(MipsPRA, "Initializing CP0 State.... ");
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PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID);
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procId.coOp = cp.CP0_PRId_CompanyOptions;
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procId.coId = cp.CP0_PRId_CompanyID;
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procId.procId = cp.CP0_PRId_ProcessorID;
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procId.rev = cp.CP0_PRId_Revision;
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setMiscRegNoEffect(MISCREG_PRID, procId);
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// Now, create Write Mask for ProcID register
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MiscReg procIDMask = 0; // Read-Only register
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replaceBits(procIDMask, 0, 32, 0);
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setRegMask(MISCREG_PRID, procIDMask);
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// Config
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ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG);
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cfg.be = cp.CP0_Config_BE;
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cfg.at = cp.CP0_Config_AT;
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cfg.ar = cp.CP0_Config_AR;
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cfg.mt = cp.CP0_Config_MT;
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cfg.vi = cp.CP0_Config_VI;
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cfg.m = 1;
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setMiscRegNoEffect(MISCREG_CONFIG, cfg);
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// Now, create Write Mask for Config register
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MiscReg cfg_Mask = 0x7FFF0007;
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replaceBits(cfg_Mask, 0, 32, 0);
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setRegMask(MISCREG_CONFIG, cfg_Mask);
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// Config1
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Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1);
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cfg1.mmuSize = cp.CP0_Config1_MMU;
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cfg1.is = cp.CP0_Config1_IS;
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cfg1.il = cp.CP0_Config1_IL;
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cfg1.ia = cp.CP0_Config1_IA;
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cfg1.ds = cp.CP0_Config1_DS;
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cfg1.dl = cp.CP0_Config1_DL;
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cfg1.da = cp.CP0_Config1_DA;
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cfg1.fp = cp.CP0_Config1_FP;
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cfg1.ep = cp.CP0_Config1_EP;
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cfg1.wr = cp.CP0_Config1_WR;
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cfg1.md = cp.CP0_Config1_MD;
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cfg1.c2 = cp.CP0_Config1_C2;
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cfg1.pc = cp.CP0_Config1_PC;
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cfg1.m = cp.CP0_Config1_M;
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setMiscRegNoEffect(MISCREG_CONFIG1, cfg1);
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// Now, create Write Mask for Config register
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MiscReg cfg1_Mask = 0; // Read Only Register
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replaceBits(cfg1_Mask, 0, 32, 0);
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setRegMask(MISCREG_CONFIG1, cfg1_Mask);
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// Config2
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Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2);
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cfg2.tu = cp.CP0_Config2_TU;
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cfg2.ts = cp.CP0_Config2_TS;
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cfg2.tl = cp.CP0_Config2_TL;
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cfg2.ta = cp.CP0_Config2_TA;
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cfg2.su = cp.CP0_Config2_SU;
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cfg2.ss = cp.CP0_Config2_SS;
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cfg2.sl = cp.CP0_Config2_SL;
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cfg2.sa = cp.CP0_Config2_SA;
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cfg2.m = cp.CP0_Config2_M;
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setMiscRegNoEffect(MISCREG_CONFIG2, cfg2);
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// Now, create Write Mask for Config register
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MiscReg cfg2_Mask = 0x7000F000; // Read Only Register
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replaceBits(cfg2_Mask, 0, 32, 0);
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setRegMask(MISCREG_CONFIG2, cfg2_Mask);
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// Config3
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Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3);
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cfg3.dspp = cp.CP0_Config3_DSPP;
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cfg3.lpa = cp.CP0_Config3_LPA;
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cfg3.veic = cp.CP0_Config3_VEIC;
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cfg3.vint = cp.CP0_Config3_VInt;
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cfg3.sp = cp.CP0_Config3_SP;
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cfg3.mt = cp.CP0_Config3_MT;
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cfg3.sm = cp.CP0_Config3_SM;
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cfg3.tl = cp.CP0_Config3_TL;
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setMiscRegNoEffect(MISCREG_CONFIG3, cfg3);
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// Now, create Write Mask for Config register
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MiscReg cfg3_Mask = 0; // Read Only Register
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replaceBits(cfg3_Mask, 0, 32, 0);
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setRegMask(MISCREG_CONFIG3, cfg3_Mask);
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// EBase - CPUNum
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EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE);
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eBase.cpuNum = cp.CP0_EBase_CPUNum;
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replaceBits(eBase, 31, 31, 1);
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setMiscRegNoEffect(MISCREG_EBASE, eBase);
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// Now, create Write Mask for Config register
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MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the
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// entire register is read only
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replaceBits(EB_Mask, 0, 32, 0);
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setRegMask(MISCREG_EBASE, EB_Mask);
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// SRS Control - HSS (Highest Shadow Set)
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SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL);
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scsCtl.hss = cp.CP0_SrsCtl_HSS;
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setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl);
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// Now, create Write Mask for the SRS Ctl register
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MiscReg SC_Mask = 0x0000F3C0;
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replaceBits(SC_Mask, 0, 32, 0);
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setRegMask(MISCREG_SRSCTL, SC_Mask);
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// IntCtl - IPTI, IPPCI
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IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL);
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intCtl.ipti = cp.CP0_IntCtl_IPTI;
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intCtl.ippci = cp.CP0_IntCtl_IPPCI;
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setMiscRegNoEffect(MISCREG_INTCTL, intCtl);
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// Now, create Write Mask for the IntCtl register
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MiscReg IC_Mask = 0x000003E0;
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replaceBits(IC_Mask, 0, 32, 0);
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setRegMask(MISCREG_INTCTL, IC_Mask);
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// Watch Hi - M - FIXME (More than 1 Watch register)
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WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0);
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watchHi.m = cp.CP0_WatchHi_M;
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setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi);
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// Now, create Write Mask for the IntCtl register
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MiscReg wh_Mask = 0x7FFF0FFF;
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replaceBits(wh_Mask, 0, 32, 0);
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setRegMask(MISCREG_WATCHHI0, wh_Mask);
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// Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
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PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0);
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perfCntCtl.m = cp.CP0_PerfCtr_M;
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perfCntCtl.w = cp.CP0_PerfCtr_W;
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setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl);
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// Now, create Write Mask for the IntCtl register
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MiscReg pc_Mask = 0x00007FF;
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replaceBits(pc_Mask, 0, 32, 0);
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setRegMask(MISCREG_PERFCNT0, pc_Mask);
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// Random
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setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63);
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// Now, create Write Mask for the IntCtl register
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MiscReg random_Mask = 0;
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replaceBits(random_Mask, 0, 32, 0);
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setRegMask(MISCREG_CP0_RANDOM, random_Mask);
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// PageGrain
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PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN);
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pageGrain.esp = cp.CP0_Config3_SP;
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setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain);
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// Now, create Write Mask for the IntCtl register
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MiscReg pg_Mask = 0x10000000;
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replaceBits(pg_Mask, 0, 32, 0);
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setRegMask(MISCREG_PAGEGRAIN, pg_Mask);
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// Status
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StatusReg status = readMiscRegNoEffect(MISCREG_STATUS);
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// Only CU0 and IE are modified on a reset - everything else needs
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// to be controlled on a per CPU model basis
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// Enable CP0 on reset
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// status.cu0 = 1;
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// Enable ERL bit on a reset
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status.erl = 1;
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// Enable BEV bit on a reset
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status.bev = 1;
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setMiscRegNoEffect(MISCREG_STATUS, status);
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// Now, create Write Mask for the Status register
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MiscReg stat_Mask = 0xFF78FF17;
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replaceBits(stat_Mask, 0, 32, 0);
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setRegMask(MISCREG_STATUS, stat_Mask);
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// MVPConf0
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MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
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mvpConf0.tca = 1;
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mvpConf0.pvpe = numVpes - 1;
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mvpConf0.ptc = numThreads - 1;
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setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0);
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// VPEConf0
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VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0);
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vpeConf0.mvp = 1;
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setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0);
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// TCBind
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for (ThreadID tid = 0; tid < numThreads; tid++) {
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TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
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tcBind.curTC = tid;
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setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
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}
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// TCHalt
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TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT);
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tcHalt.h = 0;
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setMiscRegNoEffect(MISCREG_TC_HALT, tcHalt);
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// TCStatus
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// Set TCStatus Activated to 1 for the initial thread that is running
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TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS);
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tcStatus.a = 1;
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setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
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// Set Dynamically Allocatable bit to 1 for all other threads
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for (ThreadID tid = 1; tid < numThreads; tid++) {
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tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
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tcStatus.da = 1;
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setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
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}
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MiscReg mask = 0x7FFFFFFF;
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// Now, create Write Mask for the Index register
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replaceBits(mask, 0, 32, 0);
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setRegMask(MISCREG_INDEX, mask);
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mask = 0x3FFFFFFF;
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replaceBits(mask, 0, 32, 0);
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setRegMask(MISCREG_ENTRYLO0, mask);
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setRegMask(MISCREG_ENTRYLO1, mask);
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mask = 0xFF800000;
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replaceBits(mask, 0, 32, 0);
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setRegMask(MISCREG_CONTEXT, mask);
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mask = 0x1FFFF800;
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replaceBits(mask, 0, 32, 0);
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setRegMask(MISCREG_PAGEMASK, mask);
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mask = 0x0;
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replaceBits(mask, 0, 32, 0);
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setRegMask(MISCREG_BADVADDR, mask);
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setRegMask(MISCREG_LLADDR, mask);
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mask = 0x08C00300;
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replaceBits(mask, 0, 32, 0);
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setRegMask(MISCREG_CAUSE, mask);
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}
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inline unsigned
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ISA::getVPENum(ThreadID tid)
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{
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TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
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return tcBind.curVPE;
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}
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MiscReg
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ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
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{
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unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
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? tid : getVPENum(tid);
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DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
|
|
misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
|
|
miscRegFile[misc_reg][reg_sel]);
|
|
return miscRegFile[misc_reg][reg_sel];
|
|
}
|
|
|
|
//@TODO: MIPS MT's register view automatically connects
|
|
// Status to TCStatus depending on current thread
|
|
//template <class TC>
|
|
MiscReg
|
|
ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
|
|
{
|
|
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
|
|
? tid : getVPENum(tid);
|
|
DPRINTF(MipsPRA,
|
|
"Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
|
|
misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
|
|
miscRegFile[misc_reg][reg_sel]);
|
|
|
|
return miscRegFile[misc_reg][reg_sel];
|
|
}
|
|
|
|
void
|
|
ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
|
|
{
|
|
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
|
|
? tid : getVPENum(tid);
|
|
DPRINTF(MipsPRA,
|
|
"[tid:%i]: Setting (direct set) CP0 Register:%u "
|
|
"Select:%u (%s) to %#x.\n",
|
|
tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
|
|
|
|
miscRegFile[misc_reg][reg_sel] = val;
|
|
}
|
|
|
|
void
|
|
ISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid)
|
|
{
|
|
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
|
|
? tid : getVPENum(tid);
|
|
DPRINTF(MipsPRA,
|
|
"[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
|
|
tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
|
|
miscRegFile_WriteMask[misc_reg][reg_sel] = val;
|
|
}
|
|
|
|
// PROGRAMMER'S NOTES:
|
|
// (1) Some CP0 Registers have fields that cannot
|
|
// be overwritten. Make sure to handle those particular registers
|
|
// with care!
|
|
void
|
|
ISA::setMiscReg(int misc_reg, const MiscReg &val,
|
|
ThreadContext *tc, ThreadID tid)
|
|
{
|
|
int reg_sel = (bankType[misc_reg] == perThreadContext)
|
|
? tid : getVPENum(tid);
|
|
|
|
DPRINTF(MipsPRA,
|
|
"[tid:%i]: Setting CP0 Register:%u "
|
|
"Select:%u (%s) to %#x, with effect.\n",
|
|
tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
|
|
|
|
MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);
|
|
|
|
miscRegFile[misc_reg][reg_sel] = cp0_val;
|
|
|
|
scheduleCP0Update(tc->getCpuPtr(), 1);
|
|
}
|
|
|
|
/**
|
|
* This method doesn't need to adjust the Control Register Offset
|
|
* since it has already been done in the calling method
|
|
* (setRegWithEffect)
|
|
*/
|
|
MiscReg
|
|
ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
|
|
{
|
|
MiscReg retVal = val;
|
|
|
|
// Mask off read-only regions
|
|
retVal &= miscRegFile_WriteMask[misc_reg][reg_sel];
|
|
MiscReg curVal = miscRegFile[misc_reg][reg_sel];
|
|
// Mask off current alue with inverse mask (clear writeable bits)
|
|
curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]);
|
|
retVal |= curVal; // Combine the two
|
|
DPRINTF(MipsPRA,
|
|
"filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
|
|
"current val: %lx, written val: %x\n",
|
|
miscRegFile_WriteMask[misc_reg][reg_sel],
|
|
~miscRegFile_WriteMask[misc_reg][reg_sel],
|
|
val, miscRegFile[misc_reg][reg_sel], retVal);
|
|
return retVal;
|
|
}
|
|
|
|
void
|
|
ISA::scheduleCP0Update(BaseCPU *cpu, int delay)
|
|
{
|
|
if (!cp0Updated) {
|
|
cp0Updated = true;
|
|
|
|
//schedule UPDATE
|
|
CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
|
|
cpu->schedule(cp0_event, curTick() + cpu->ticks(delay));
|
|
}
|
|
}
|
|
|
|
void
|
|
ISA::updateCPU(BaseCPU *cpu)
|
|
{
|
|
///////////////////////////////////////////////////////////////////
|
|
//
|
|
// EVALUATE CP0 STATE FOR MIPS MT
|
|
//
|
|
///////////////////////////////////////////////////////////////////
|
|
MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
|
|
ThreadID num_threads = mvpConf0.ptc + 1;
|
|
|
|
for (ThreadID tid = 0; tid < num_threads; tid++) {
|
|
TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
|
|
TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT, tid);
|
|
|
|
//@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
|
|
if (tcHalt.h == 1 || tcStatus.a == 0) {
|
|
haltThread(cpu->getContext(tid));
|
|
} else if (tcHalt.h == 0 && tcStatus.a == 1) {
|
|
restoreThread(cpu->getContext(tid));
|
|
}
|
|
}
|
|
|
|
num_threads = mvpConf0.ptc + 1;
|
|
|
|
// Toggle update flag after we finished updating
|
|
cp0Updated = false;
|
|
}
|
|
|
|
ISA::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type)
|
|
: Event(CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type)
|
|
{ }
|
|
|
|
void
|
|
ISA::CP0Event::process()
|
|
{
|
|
switch (cp0EventType)
|
|
{
|
|
case UpdateCP0:
|
|
cp0->updateCPU(cpu);
|
|
break;
|
|
}
|
|
}
|
|
|
|
const char *
|
|
ISA::CP0Event::description() const
|
|
{
|
|
return "Coprocessor-0 event";
|
|
}
|
|
|
|
void
|
|
ISA::CP0Event::scheduleEvent(int delay)
|
|
{
|
|
cpu->reschedule(this, curTick() + cpu->ticks(delay), true);
|
|
}
|
|
|
|
void
|
|
ISA::CP0Event::unscheduleEvent()
|
|
{
|
|
if (scheduled())
|
|
squash();
|
|
}
|
|
|
|
}
|