1709 lines
48 KiB
C++
1709 lines
48 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#include "config/the_isa.hh"
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#include "config/use_checker.hh"
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#include "cpu/ozone/lw_back_end.hh"
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#include "cpu/op_class.hh"
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#if USE_CHECKER
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#include "cpu/checker/cpu.hh"
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#endif
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template <class Impl>
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void
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LWBackEnd<Impl>::generateTrapEvent(Tick latency)
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{
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DPRINTF(BE, "Generating trap event\n");
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TrapEvent *trap = new TrapEvent(this);
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trap->schedule(curTick() + cpu->ticks(latency));
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thread->trapPending = true;
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}
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template <class Impl>
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int
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LWBackEnd<Impl>::wakeDependents(DynInstPtr &inst, bool memory_deps)
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{
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assert(!inst->isSquashed());
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std::vector<DynInstPtr> &dependents = memory_deps ? inst->getMemDeps() :
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inst->getDependents();
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int num_outputs = dependents.size();
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DPRINTF(BE, "Waking instruction [sn:%lli] dependents in IQ\n", inst->seqNum);
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for (int i = 0; i < num_outputs; i++) {
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DynInstPtr dep_inst = dependents[i];
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if (!memory_deps) {
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dep_inst->markSrcRegReady();
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} else {
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if (!dep_inst->isSquashed())
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dep_inst->markMemInstReady(inst.get());
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}
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DPRINTF(BE, "Marking source reg ready [sn:%lli] in IQ\n", dep_inst->seqNum);
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if (dep_inst->readyToIssue() && dep_inst->isInROB() &&
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!dep_inst->isNonSpeculative() && !dep_inst->isStoreConditional() &&
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dep_inst->memDepReady() && !dep_inst->isMemBarrier() &&
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!dep_inst->isWriteBarrier()) {
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DPRINTF(BE, "Adding instruction to exeList [sn:%lli]\n",
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dep_inst->seqNum);
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exeList.push(dep_inst);
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if (dep_inst->iqItValid) {
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DPRINTF(BE, "Removing instruction from waiting list\n");
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waitingList.erase(dep_inst->iqIt);
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waitingInsts--;
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dep_inst->iqItValid = false;
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assert(waitingInsts >= 0);
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}
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if (dep_inst->isMemRef()) {
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removeWaitingMemOp(dep_inst);
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DPRINTF(BE, "Issued a waiting mem op [sn:%lli]\n",
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dep_inst->seqNum);
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}
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}
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}
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return num_outputs;
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}
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template <class Impl>
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void
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LWBackEnd<Impl>::rescheduleMemInst(DynInstPtr &inst)
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{
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replayList.push_front(inst);
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}
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template <class Impl>
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LWBackEnd<Impl>::TrapEvent::TrapEvent(LWBackEnd<Impl> *_be)
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: Event(&mainEventQueue, CPU_Tick_Pri), be(_be)
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{
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this->setFlags(Event::AutoDelete);
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}
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template <class Impl>
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void
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LWBackEnd<Impl>::TrapEvent::process()
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{
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be->trapSquash = true;
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}
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template <class Impl>
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const char *
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LWBackEnd<Impl>::TrapEvent::description() const
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{
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return "Trap";
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}
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template <class Impl>
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void
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LWBackEnd<Impl>::replayMemInst(DynInstPtr &inst)
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{
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bool found_inst = false;
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while (!replayList.empty()) {
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exeList.push(replayList.front());
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if (replayList.front() == inst) {
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found_inst = true;
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}
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replayList.pop_front();
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}
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assert(found_inst);
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}
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template <class Impl>
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LWBackEnd<Impl>::LWBackEnd(Params *params)
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: d2i(5, 5), i2e(5, 5), e2c(5, 5), numInstsToWB(params->backEndLatency, 0),
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trapSquash(false), tcSquash(false),
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latency(params->backEndLatency),
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width(params->backEndWidth), lsqLimits(params->lsqLimits),
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exactFullStall(true)
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{
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numROBEntries = params->numROBEntries;
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numInsts = 0;
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maxOutstandingMemOps = params->maxOutstandingMemOps;
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numWaitingMemOps = 0;
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waitingInsts = 0;
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switchedOut = false;
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switchPending = false;
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LSQ.setBE(this);
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// Setup IQ and LSQ with their parameters here.
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instsToDispatch = d2i.getWire(-1);
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instsToExecute = i2e.getWire(-1);
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dispatchWidth = params->dispatchWidth ? params->dispatchWidth : width;
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issueWidth = params->issueWidth ? params->issueWidth : width;
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wbWidth = params->wbWidth ? params->wbWidth : width;
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commitWidth = params->commitWidth ? params->commitWidth : width;
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LSQ.init(params, params->LQEntries, params->SQEntries, 0);
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dispatchStatus = Running;
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commitStatus = Running;
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}
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template <class Impl>
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std::string
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LWBackEnd<Impl>::name() const
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{
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return cpu->name() + ".backend";
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}
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template <class Impl>
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void
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LWBackEnd<Impl>::regStats()
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{
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using namespace Stats;
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LSQ.regStats();
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robCapEvents
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.init(cpu->numThreads)
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.name(name() + ".ROB:cap_events")
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.desc("number of cycles where ROB cap was active")
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.flags(total)
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;
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robCapInstCount
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.init(cpu->numThreads)
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.name(name() + ".ROB:cap_inst")
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.desc("number of instructions held up by ROB cap")
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.flags(total)
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;
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iqCapEvents
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.init(cpu->numThreads)
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.name(name() +".IQ:cap_events" )
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.desc("number of cycles where IQ cap was active")
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.flags(total)
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;
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iqCapInstCount
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.init(cpu->numThreads)
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.name(name() + ".IQ:cap_inst")
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.desc("number of instructions held up by IQ cap")
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.flags(total)
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;
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exeInst
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.init(cpu->numThreads)
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.name(name() + ".ISSUE:count")
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.desc("number of insts issued")
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.flags(total)
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;
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exeSwp
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.init(cpu->numThreads)
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.name(name() + ".ISSUE:swp")
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.desc("number of swp insts issued")
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.flags(total)
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;
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exeNop
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.init(cpu->numThreads)
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.name(name() + ".ISSUE:nop")
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.desc("number of nop insts issued")
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.flags(total)
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;
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exeRefs
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.init(cpu->numThreads)
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.name(name() + ".ISSUE:refs")
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.desc("number of memory reference insts issued")
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.flags(total)
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;
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exeLoads
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.init(cpu->numThreads)
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.name(name() + ".ISSUE:loads")
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.desc("number of load insts issued")
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.flags(total)
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;
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exeBranches
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.init(cpu->numThreads)
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.name(name() + ".ISSUE:branches")
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.desc("Number of branches issued")
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.flags(total)
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;
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issuedOps
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.init(cpu->numThreads)
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.name(name() + ".ISSUE:op_count")
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.desc("number of insts issued")
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.flags(total)
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;
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/*
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for (int i=0; i<Num_OpClasses; ++i) {
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stringstream subname;
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subname << opClassStrings[i] << "_delay";
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issue_delay_dist.subname(i, subname.str());
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}
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*/
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//
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// Other stats
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//
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lsqForwLoads
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.init(cpu->numThreads)
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.name(name() + ".LSQ:forw_loads")
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.desc("number of loads forwarded via LSQ")
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.flags(total)
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;
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invAddrLoads
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.init(cpu->numThreads)
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.name(name() + ".ISSUE:addr_loads")
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.desc("number of invalid-address loads")
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.flags(total)
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;
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invAddrSwpfs
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.init(cpu->numThreads)
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.name(name() + ".ISSUE:addr_swpfs")
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.desc("number of invalid-address SW prefetches")
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.flags(total)
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;
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lsqBlockedLoads
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.init(cpu->numThreads)
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.name(name() + ".LSQ:blocked_loads")
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.desc("number of ready loads not issued due to memory disambiguation")
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.flags(total)
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;
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lsqInversion
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.name(name() + ".ISSUE:lsq_invert")
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.desc("Number of times LSQ instruction issued early")
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;
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nIssuedDist
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.init(issueWidth + 1)
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.name(name() + ".ISSUE:issued_per_cycle")
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.desc("Number of insts issued each cycle")
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.flags(total | pdf | dist)
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;
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/*
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issueDelayDist
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.init(Num_OpClasses,0,99,2)
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.name(name() + ".ISSUE:")
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.desc("cycles from operands ready to issue")
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.flags(pdf | cdf)
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;
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queueResDist
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.init(Num_OpClasses, 0, 99, 2)
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.name(name() + ".IQ:residence:")
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.desc("cycles from dispatch to issue")
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.flags(total | pdf | cdf )
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;
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for (int i = 0; i < Num_OpClasses; ++i) {
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queueResDist.subname(i, opClassStrings[i]);
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}
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*/
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writebackCount
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.init(cpu->numThreads)
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.name(name() + ".WB:count")
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.desc("cumulative count of insts written-back")
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.flags(total)
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;
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producerInst
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.init(cpu->numThreads)
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.name(name() + ".WB:producers")
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.desc("num instructions producing a value")
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.flags(total)
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;
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consumerInst
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.init(cpu->numThreads)
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.name(name() + ".WB:consumers")
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.desc("num instructions consuming a value")
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.flags(total)
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;
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wbPenalized
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.init(cpu->numThreads)
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.name(name() + ".WB:penalized")
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.desc("number of instrctions required to write to 'other' IQ")
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.flags(total)
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;
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wbPenalizedRate
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.name(name() + ".WB:penalized_rate")
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.desc ("fraction of instructions written-back that wrote to 'other' IQ")
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.flags(total)
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;
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wbPenalizedRate = wbPenalized / writebackCount;
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wbFanout
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.name(name() + ".WB:fanout")
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.desc("average fanout of values written-back")
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.flags(total)
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;
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wbFanout = producerInst / consumerInst;
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wbRate
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.name(name() + ".WB:rate")
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.desc("insts written-back per cycle")
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.flags(total)
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;
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wbRate = writebackCount / cpu->numCycles;
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statComInst
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.init(cpu->numThreads)
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.name(name() + ".COM:count")
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.desc("Number of instructions committed")
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.flags(total)
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;
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statComSwp
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.init(cpu->numThreads)
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.name(name() + ".COM:swp_count")
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.desc("Number of s/w prefetches committed")
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.flags(total)
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;
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statComRefs
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.init(cpu->numThreads)
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.name(name() + ".COM:refs")
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.desc("Number of memory references committed")
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.flags(total)
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;
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statComLoads
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.init(cpu->numThreads)
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.name(name() + ".COM:loads")
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.desc("Number of loads committed")
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.flags(total)
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;
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statComMembars
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.init(cpu->numThreads)
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.name(name() + ".COM:membars")
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.desc("Number of memory barriers committed")
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.flags(total)
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;
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statComBranches
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.init(cpu->numThreads)
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.name(name() + ".COM:branches")
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.desc("Number of branches committed")
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.flags(total)
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;
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nCommittedDist
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.init(0,commitWidth,1)
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.name(name() + ".COM:committed_per_cycle")
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.desc("Number of insts commited each cycle")
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.flags(pdf)
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;
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//
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// Commit-Eligible instructions...
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//
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// -> The number of instructions eligible to commit in those
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// cycles where we reached our commit BW limit (less the number
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// actually committed)
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//
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// -> The average value is computed over ALL CYCLES... not just
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// the BW limited cycles
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//
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// -> The standard deviation is computed only over cycles where
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// we reached the BW limit
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//
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commitEligible
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.init(cpu->numThreads)
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.name(name() + ".COM:bw_limited")
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.desc("number of insts not committed due to BW limits")
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.flags(total)
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;
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commitEligibleSamples
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.name(name() + ".COM:bw_lim_events")
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.desc("number cycles where commit BW limit reached")
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;
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squashedInsts
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.init(cpu->numThreads)
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.name(name() + ".COM:squashed_insts")
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.desc("Number of instructions removed from inst list")
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;
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ROBSquashedInsts
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.init(cpu->numThreads)
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.name(name() + ".COM:rob_squashed_insts")
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.desc("Number of instructions removed from inst list when they reached the head of the ROB")
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;
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ROBFcount
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.name(name() + ".ROB:full_count")
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.desc("number of cycles where ROB was full")
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;
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ROBCount
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.init(cpu->numThreads)
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.name(name() + ".ROB:occupancy")
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.desc(name() + ".ROB occupancy (cumulative)")
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.flags(total)
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;
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ROBFullRate
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.name(name() + ".ROB:full_rate")
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.desc("ROB full per cycle")
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;
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ROBFullRate = ROBFcount / cpu->numCycles;
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ROBOccRate
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.name(name() + ".ROB:occ_rate")
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.desc("ROB occupancy rate")
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.flags(total)
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;
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ROBOccRate = ROBCount / cpu->numCycles;
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/*
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ROBOccDist
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.init(cpu->numThreads, 0, numROBEntries, 2)
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.name(name() + ".ROB:occ_dist")
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.desc("ROB Occupancy per cycle")
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.flags(total | cdf)
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;
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*/
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}
|
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|
|
template <class Impl>
|
|
void
|
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LWBackEnd<Impl>::setCPU(OzoneCPU *cpu_ptr)
|
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{
|
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cpu = cpu_ptr;
|
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LSQ.setCPU(cpu_ptr);
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checker = cpu->checker;
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}
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|
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template <class Impl>
|
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void
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LWBackEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
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{
|
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comm = _comm;
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toIEW = comm->getWire(0);
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fromCommit = comm->getWire(-1);
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}
|
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|
|
#if FULL_SYSTEM
|
|
template <class Impl>
|
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void
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LWBackEnd<Impl>::checkInterrupts()
|
|
{
|
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if (cpu->checkInterrupts(tc) && !trapSquash && !tcSquash) {
|
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frontEnd->interruptPending = true;
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if (robEmpty() && !LSQ.hasStoresToWB()) {
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// Will need to squash all instructions currently in flight and have
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// the interrupt handler restart at the last non-committed inst.
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// Most of that can be handled through the trap() function. The
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// processInterrupts() function really just checks for interrupts
|
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// and then calls trap() if there is an interrupt present.
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|
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// Not sure which thread should be the one to interrupt. For now
|
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// always do thread 0.
|
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assert(!thread->inSyscall);
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thread->inSyscall = true;
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|
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// CPU will handle implementation of the interrupt.
|
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cpu->processInterrupts();
|
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|
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// Now squash or record that I need to squash this cycle.
|
|
commitStatus = TrapPending;
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|
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// Exit state update mode to avoid accidental updating.
|
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thread->inSyscall = false;
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|
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// Generate trap squash event.
|
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generateTrapEvent();
|
|
|
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DPRINTF(BE, "Interrupt detected.\n");
|
|
} else {
|
|
DPRINTF(BE, "Interrupt must wait for ROB to drain.\n");
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::handleFault(Fault &fault, Tick latency)
|
|
{
|
|
DPRINTF(BE, "Handling fault!\n");
|
|
|
|
assert(!thread->inSyscall);
|
|
|
|
thread->inSyscall = true;
|
|
|
|
// Consider holding onto the trap and waiting until the trap event
|
|
// happens for this to be executed.
|
|
fault->invoke(thread->getTC());
|
|
|
|
// Exit state update mode to avoid accidental updating.
|
|
thread->inSyscall = false;
|
|
|
|
commitStatus = TrapPending;
|
|
|
|
// Generate trap squash event.
|
|
generateTrapEvent(latency);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::tick()
|
|
{
|
|
DPRINTF(BE, "Ticking back end\n");
|
|
|
|
// Read in any done instruction information and update the IQ or LSQ.
|
|
updateStructures();
|
|
|
|
if (switchPending && robEmpty() && !LSQ.hasStoresToWB()) {
|
|
cpu->signalSwitched();
|
|
return;
|
|
}
|
|
|
|
readyInstsForCommit();
|
|
|
|
numInstsToWB.advance();
|
|
|
|
ROBCount[0]+= numInsts;
|
|
|
|
wbCycle = 0;
|
|
|
|
#if FULL_SYSTEM
|
|
checkInterrupts();
|
|
#endif
|
|
|
|
if (trapSquash) {
|
|
assert(!tcSquash);
|
|
squashFromTrap();
|
|
} else if (tcSquash) {
|
|
squashFromTC();
|
|
}
|
|
|
|
if (dispatchStatus != Blocked) {
|
|
dispatchInsts();
|
|
} else {
|
|
checkDispatchStatus();
|
|
}
|
|
|
|
if (commitStatus != TrapPending) {
|
|
executeInsts();
|
|
|
|
commitInsts();
|
|
}
|
|
|
|
LSQ.writebackStores();
|
|
|
|
DPRINTF(BE, "Waiting insts: %i, mem ops: %i, ROB entries in use: %i, "
|
|
"LSQ loads: %i, LSQ stores: %i\n",
|
|
waitingInsts, numWaitingMemOps, numInsts,
|
|
LSQ.numLoads(), LSQ.numStores());
|
|
|
|
#ifdef DEBUG
|
|
assert(numInsts == instList.size());
|
|
assert(waitingInsts == waitingList.size());
|
|
assert(numWaitingMemOps == waitingMemOps.size());
|
|
assert(!switchedOut);
|
|
#endif
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::updateStructures()
|
|
{
|
|
if (fromCommit->doneSeqNum) {
|
|
LSQ.commitLoads(fromCommit->doneSeqNum);
|
|
LSQ.commitStores(fromCommit->doneSeqNum);
|
|
}
|
|
|
|
if (fromCommit->nonSpecSeqNum) {
|
|
if (fromCommit->uncached) {
|
|
// LSQ.executeLoad(fromCommit->lqIdx);
|
|
} else {
|
|
// IQ.scheduleNonSpec(
|
|
// fromCommit->nonSpecSeqNum);
|
|
}
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::addToLSQ(DynInstPtr &inst)
|
|
{
|
|
// Do anything LSQ specific here?
|
|
LSQ.insert(inst);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::dispatchInsts()
|
|
{
|
|
DPRINTF(BE, "Trying to dispatch instructions.\n");
|
|
|
|
while (numInsts < numROBEntries &&
|
|
numWaitingMemOps < maxOutstandingMemOps) {
|
|
// Get instruction from front of time buffer
|
|
if (lsqLimits && LSQ.isFull()) {
|
|
break;
|
|
}
|
|
|
|
DynInstPtr inst = frontEnd->getInst();
|
|
if (!inst) {
|
|
break;
|
|
} else if (inst->isSquashed()) {
|
|
continue;
|
|
}
|
|
|
|
++numInsts;
|
|
instList.push_front(inst);
|
|
|
|
inst->setInROB();
|
|
|
|
DPRINTF(BE, "Dispatching instruction [sn:%lli] PC:%#x\n",
|
|
inst->seqNum, inst->readPC());
|
|
|
|
for (int i = 0; i < inst->numDestRegs(); ++i)
|
|
renameTable[inst->destRegIdx(i)] = inst;
|
|
|
|
if (inst->isMemBarrier() || inst->isWriteBarrier()) {
|
|
if (memBarrier) {
|
|
DPRINTF(BE, "Instruction [sn:%lli] is waiting on "
|
|
"barrier [sn:%lli].\n",
|
|
inst->seqNum, memBarrier->seqNum);
|
|
memBarrier->addMemDependent(inst);
|
|
inst->addSrcMemInst(memBarrier);
|
|
}
|
|
memBarrier = inst;
|
|
inst->setCanCommit();
|
|
} else if (inst->readyToIssue() &&
|
|
!inst->isNonSpeculative() &&
|
|
!inst->isStoreConditional()) {
|
|
if (inst->isMemRef()) {
|
|
|
|
LSQ.insert(inst);
|
|
if (memBarrier) {
|
|
DPRINTF(BE, "Instruction [sn:%lli] is waiting on "
|
|
"barrier [sn:%lli].\n",
|
|
inst->seqNum, memBarrier->seqNum);
|
|
memBarrier->addMemDependent(inst);
|
|
inst->addSrcMemInst(memBarrier);
|
|
addWaitingMemOp(inst);
|
|
|
|
waitingList.push_front(inst);
|
|
inst->iqIt = waitingList.begin();
|
|
inst->iqItValid = true;
|
|
waitingInsts++;
|
|
} else {
|
|
DPRINTF(BE, "Instruction [sn:%lli] ready, addding to "
|
|
"exeList.\n",
|
|
inst->seqNum);
|
|
exeList.push(inst);
|
|
}
|
|
} else if (inst->isNop()) {
|
|
DPRINTF(BE, "Nop encountered [sn:%lli], skipping exeList.\n",
|
|
inst->seqNum);
|
|
inst->setIssued();
|
|
inst->setExecuted();
|
|
inst->setCanCommit();
|
|
numInstsToWB[0]++;
|
|
} else {
|
|
DPRINTF(BE, "Instruction [sn:%lli] ready, addding to "
|
|
"exeList.\n",
|
|
inst->seqNum);
|
|
exeList.push(inst);
|
|
}
|
|
} else {
|
|
if (inst->isNonSpeculative() || inst->isStoreConditional()) {
|
|
inst->setCanCommit();
|
|
DPRINTF(BE, "Adding non speculative instruction\n");
|
|
}
|
|
|
|
if (inst->isMemRef()) {
|
|
addWaitingMemOp(inst);
|
|
LSQ.insert(inst);
|
|
if (memBarrier) {
|
|
memBarrier->addMemDependent(inst);
|
|
inst->addSrcMemInst(memBarrier);
|
|
|
|
DPRINTF(BE, "Instruction [sn:%lli] is waiting on "
|
|
"barrier [sn:%lli].\n",
|
|
inst->seqNum, memBarrier->seqNum);
|
|
}
|
|
}
|
|
|
|
DPRINTF(BE, "Instruction [sn:%lli] not ready, addding to "
|
|
"waitingList.\n",
|
|
inst->seqNum);
|
|
waitingList.push_front(inst);
|
|
inst->iqIt = waitingList.begin();
|
|
inst->iqItValid = true;
|
|
waitingInsts++;
|
|
}
|
|
}
|
|
|
|
// Check if IQ or LSQ is full. If so we'll need to break and stop
|
|
// removing instructions. Also update the number of insts to remove
|
|
// from the queue. Check here if we don't care about exact stall
|
|
// conditions.
|
|
/*
|
|
bool stall = false;
|
|
if (IQ.isFull()) {
|
|
DPRINTF(BE, "IQ is full!\n");
|
|
stall = true;
|
|
} else if (LSQ.isFull()) {
|
|
DPRINTF(BE, "LSQ is full!\n");
|
|
stall = true;
|
|
} else if (isFull()) {
|
|
DPRINTF(BE, "ROB is full!\n");
|
|
stall = true;
|
|
ROB_fcount++;
|
|
}
|
|
if (stall) {
|
|
d2i.advance();
|
|
dispatchStall();
|
|
return;
|
|
}
|
|
*/
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::dispatchStall()
|
|
{
|
|
dispatchStatus = Blocked;
|
|
if (!cpu->decoupledFrontEnd) {
|
|
// Tell front end to stall here through a timebuffer, or just tell
|
|
// it directly.
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::checkDispatchStatus()
|
|
{
|
|
DPRINTF(BE, "Checking dispatch status\n");
|
|
assert(dispatchStatus == Blocked);
|
|
if (!LSQ.isFull() && !isFull()) {
|
|
DPRINTF(BE, "Dispatch no longer blocked\n");
|
|
dispatchStatus = Running;
|
|
dispatchInsts();
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::executeInsts()
|
|
{
|
|
DPRINTF(BE, "Trying to execute instructions\n");
|
|
|
|
int num_executed = 0;
|
|
while (!exeList.empty() && num_executed < issueWidth) {
|
|
DynInstPtr inst = exeList.top();
|
|
|
|
DPRINTF(BE, "Executing inst [sn:%lli] PC: %#x\n",
|
|
inst->seqNum, inst->readPC());
|
|
|
|
// Check if the instruction is squashed; if so then skip it
|
|
// and don't count it towards the FU usage.
|
|
if (inst->isSquashed()) {
|
|
DPRINTF(BE, "Execute: Instruction was squashed.\n");
|
|
|
|
// Not sure how to handle this plus the method of sending # of
|
|
// instructions to use. Probably will just have to count it
|
|
// towards the bandwidth usage, but not the FU usage.
|
|
++num_executed;
|
|
|
|
// Consider this instruction executed so that commit can go
|
|
// ahead and retire the instruction.
|
|
inst->setExecuted();
|
|
|
|
// Not sure if I should set this here or just let commit try to
|
|
// commit any squashed instructions. I like the latter a bit more.
|
|
inst->setCanCommit();
|
|
|
|
// ++iewExecSquashedInsts;
|
|
exeList.pop();
|
|
|
|
continue;
|
|
}
|
|
|
|
Fault fault = NoFault;
|
|
|
|
// Execute instruction.
|
|
// Note that if the instruction faults, it will be handled
|
|
// at the commit stage.
|
|
if (inst->isMemRef() &&
|
|
(!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
|
|
DPRINTF(BE, "Execute: Initiating access for memory "
|
|
"reference.\n");
|
|
|
|
if (inst->isLoad()) {
|
|
LSQ.executeLoad(inst);
|
|
} else if (inst->isStore()) {
|
|
Fault fault = LSQ.executeStore(inst);
|
|
|
|
if (!inst->isStoreConditional() && fault == NoFault) {
|
|
inst->setExecuted();
|
|
|
|
instToCommit(inst);
|
|
} else if (fault != NoFault) {
|
|
// If the instruction faulted, then we need to send it along to commit
|
|
// without the instruction completing.
|
|
// Send this instruction to commit, also make sure iew stage
|
|
// realizes there is activity.
|
|
inst->setExecuted();
|
|
|
|
instToCommit(inst);
|
|
}
|
|
} else {
|
|
panic("Unknown mem type!");
|
|
}
|
|
} else {
|
|
inst->execute();
|
|
|
|
inst->setExecuted();
|
|
|
|
instToCommit(inst);
|
|
}
|
|
|
|
updateExeInstStats(inst);
|
|
|
|
++funcExeInst;
|
|
++num_executed;
|
|
|
|
exeList.pop();
|
|
|
|
if (inst->mispredicted()) {
|
|
squashDueToBranch(inst);
|
|
break;
|
|
} else if (LSQ.violation()) {
|
|
// Get the DynInst that caused the violation. Note that this
|
|
// clears the violation signal.
|
|
DynInstPtr violator;
|
|
violator = LSQ.getMemDepViolator();
|
|
|
|
DPRINTF(BE, "LDSTQ detected a violation. Violator PC: "
|
|
"%#x, inst PC: %#x. Addr is: %#x.\n",
|
|
violator->readPC(), inst->readPC(), inst->physEffAddr);
|
|
|
|
// Squash.
|
|
squashDueToMemViolation(inst);
|
|
}
|
|
}
|
|
|
|
issuedOps[0]+= num_executed;
|
|
nIssuedDist[num_executed]++;
|
|
}
|
|
|
|
template<class Impl>
|
|
void
|
|
LWBackEnd<Impl>::instToCommit(DynInstPtr &inst)
|
|
{
|
|
DPRINTF(BE, "Sending instructions to commit [sn:%lli] PC %#x.\n",
|
|
inst->seqNum, inst->readPC());
|
|
|
|
if (!inst->isSquashed()) {
|
|
if (inst->isExecuted()) {
|
|
inst->setResultReady();
|
|
int dependents = wakeDependents(inst);
|
|
if (dependents) {
|
|
producerInst[0]++;
|
|
consumerInst[0]+= dependents;
|
|
}
|
|
}
|
|
}
|
|
|
|
writeback.push_back(inst);
|
|
|
|
numInstsToWB[0]++;
|
|
|
|
writebackCount[0]++;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::readyInstsForCommit()
|
|
{
|
|
for (int i = numInstsToWB[-latency];
|
|
!writeback.empty() && i;
|
|
--i)
|
|
{
|
|
DynInstPtr inst = writeback.front();
|
|
writeback.pop_front();
|
|
if (!inst->isSquashed()) {
|
|
DPRINTF(BE, "Writing back instruction [sn:%lli] PC %#x.\n",
|
|
inst->seqNum, inst->readPC());
|
|
|
|
inst->setCanCommit();
|
|
}
|
|
}
|
|
}
|
|
|
|
#if 0
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::writebackInsts()
|
|
{
|
|
int wb_width = wbWidth;
|
|
// Using this method I'm not quite sure how to prevent an
|
|
// instruction from waking its own dependents multiple times,
|
|
// without the guarantee that commit always has enough bandwidth
|
|
// to accept all instructions being written back. This guarantee
|
|
// might not be too unrealistic.
|
|
InstListIt wb_inst_it = writeback.begin();
|
|
InstListIt wb_end_it = writeback.end();
|
|
int inst_num = 0;
|
|
int consumer_insts = 0;
|
|
|
|
for (; inst_num < wb_width &&
|
|
wb_inst_it != wb_end_it; inst_num++) {
|
|
DynInstPtr inst = (*wb_inst_it);
|
|
|
|
// Some instructions will be sent to commit without having
|
|
// executed because they need commit to handle them.
|
|
// E.g. Uncached loads have not actually executed when they
|
|
// are first sent to commit. Instead commit must tell the LSQ
|
|
// when it's ready to execute the uncached load.
|
|
if (!inst->isSquashed()) {
|
|
DPRINTF(BE, "Writing back instruction [sn:%lli] PC %#x.\n",
|
|
inst->seqNum, inst->readPC());
|
|
|
|
inst->setCanCommit();
|
|
inst->setResultReady();
|
|
|
|
if (inst->isExecuted()) {
|
|
int dependents = wakeDependents(inst);
|
|
if (dependents) {
|
|
producer_inst[0]++;
|
|
consumer_insts+= dependents;
|
|
}
|
|
}
|
|
}
|
|
|
|
writeback.erase(wb_inst_it++);
|
|
}
|
|
LSQ.writebackStores();
|
|
consumer_inst[0]+= consumer_insts;
|
|
writeback_count[0]+= inst_num;
|
|
}
|
|
#endif
|
|
template <class Impl>
|
|
bool
|
|
LWBackEnd<Impl>::commitInst(int inst_num)
|
|
{
|
|
// Read instruction from the head of the ROB
|
|
DynInstPtr inst = instList.back();
|
|
|
|
// Make sure instruction is valid
|
|
assert(inst);
|
|
|
|
if (!inst->readyToCommit())
|
|
return false;
|
|
|
|
DPRINTF(BE, "Trying to commit instruction [sn:%lli] PC:%#x\n",
|
|
inst->seqNum, inst->readPC());
|
|
|
|
thread->setPC(inst->readPC());
|
|
thread->setNextPC(inst->readNextPC());
|
|
inst->setAtCommit();
|
|
|
|
// If the instruction is not executed yet, then it is a non-speculative
|
|
// or store inst. Signal backwards that it should be executed.
|
|
if (!inst->isExecuted()) {
|
|
if (inst->isNonSpeculative() ||
|
|
(inst->isStoreConditional() && inst->getFault() == NoFault) ||
|
|
inst->isMemBarrier() ||
|
|
inst->isWriteBarrier()) {
|
|
#if !FULL_SYSTEM
|
|
// Hack to make sure syscalls aren't executed until all stores
|
|
// write back their data. This direct communication shouldn't
|
|
// be used for anything other than this.
|
|
if (inst_num > 0 || LSQ.hasStoresToWB())
|
|
#else
|
|
if ((inst->isMemBarrier() || inst->isWriteBarrier() ||
|
|
inst->isQuiesce()) &&
|
|
LSQ.hasStoresToWB())
|
|
#endif
|
|
{
|
|
DPRINTF(BE, "Waiting for all stores to writeback.\n");
|
|
return false;
|
|
}
|
|
|
|
DPRINTF(BE, "Encountered a store or non-speculative "
|
|
"instruction at the head of the ROB, PC %#x.\n",
|
|
inst->readPC());
|
|
|
|
if (inst->isMemBarrier() || inst->isWriteBarrier()) {
|
|
DPRINTF(BE, "Waking dependents on barrier [sn:%lli]\n",
|
|
inst->seqNum);
|
|
assert(memBarrier);
|
|
wakeDependents(inst, true);
|
|
if (memBarrier == inst)
|
|
memBarrier = NULL;
|
|
inst->clearMemDependents();
|
|
}
|
|
|
|
// Send back the non-speculative instruction's sequence number.
|
|
if (inst->iqItValid) {
|
|
DPRINTF(BE, "Removing instruction from waiting list\n");
|
|
waitingList.erase(inst->iqIt);
|
|
inst->iqItValid = false;
|
|
waitingInsts--;
|
|
assert(waitingInsts >= 0);
|
|
if (inst->isStore())
|
|
removeWaitingMemOp(inst);
|
|
}
|
|
|
|
exeList.push(inst);
|
|
|
|
// Change the instruction so it won't try to commit again until
|
|
// it is executed.
|
|
inst->clearCanCommit();
|
|
|
|
// ++commitNonSpecStalls;
|
|
|
|
return false;
|
|
} else if (inst->isLoad()) {
|
|
DPRINTF(BE, "[sn:%lli]: Uncached load, PC %#x.\n",
|
|
inst->seqNum, inst->readPC());
|
|
|
|
// Send back the non-speculative instruction's sequence
|
|
// number. Maybe just tell the lsq to re-execute the load.
|
|
|
|
// Send back the non-speculative instruction's sequence number.
|
|
if (inst->iqItValid) {
|
|
DPRINTF(BE, "Removing instruction from waiting list\n");
|
|
waitingList.erase(inst->iqIt);
|
|
inst->iqItValid = false;
|
|
waitingInsts--;
|
|
assert(waitingInsts >= 0);
|
|
removeWaitingMemOp(inst);
|
|
}
|
|
replayMemInst(inst);
|
|
|
|
inst->clearCanCommit();
|
|
|
|
return false;
|
|
} else {
|
|
panic("Trying to commit un-executed instruction "
|
|
"of unknown type!\n");
|
|
}
|
|
}
|
|
|
|
// Not handled for now.
|
|
assert(!inst->isThreadSync());
|
|
assert(inst->memDepReady());
|
|
// Stores will mark themselves as totally completed as they need
|
|
// to wait to writeback to memory. @todo: Hack...attempt to fix
|
|
// having the checker be forced to wait until a store completes in
|
|
// order to check all of the instructions. If the store at the
|
|
// head of the check list misses, but a later store hits, then
|
|
// loads in the checker may see the younger store values instead
|
|
// of the store they should see. Either the checker needs its own
|
|
// memory (annoying to update), its own store buffer (how to tell
|
|
// which value is correct?), or something else...
|
|
if (!inst->isStore()) {
|
|
inst->setCompleted();
|
|
}
|
|
// Check if the instruction caused a fault. If so, trap.
|
|
Fault inst_fault = inst->getFault();
|
|
|
|
// Use checker prior to updating anything due to traps or PC
|
|
// based events.
|
|
#if USE_CHECKER
|
|
if (checker) {
|
|
checker->verify(inst);
|
|
}
|
|
#endif
|
|
|
|
if (inst_fault != NoFault) {
|
|
DPRINTF(BE, "Inst [sn:%lli] PC %#x has a fault\n",
|
|
inst->seqNum, inst->readPC());
|
|
|
|
// Instruction is completed as it has a fault.
|
|
inst->setCompleted();
|
|
|
|
if (LSQ.hasStoresToWB()) {
|
|
DPRINTF(BE, "Stores still in flight, will wait until drained.\n");
|
|
return false;
|
|
} else if (inst_num != 0) {
|
|
DPRINTF(BE, "Will wait until instruction is head of commit group.\n");
|
|
return false;
|
|
}
|
|
#if USE_CHECKER
|
|
else if (checker && inst->isStore()) {
|
|
checker->verify(inst);
|
|
}
|
|
#endif
|
|
|
|
handleFault(inst_fault);
|
|
return false;
|
|
}
|
|
|
|
int freed_regs = 0;
|
|
|
|
for (int i = 0; i < inst->numDestRegs(); ++i) {
|
|
DPRINTF(BE, "Commit rename map setting reg %i to [sn:%lli]\n",
|
|
(int)inst->destRegIdx(i), inst->seqNum);
|
|
thread->renameTable[inst->destRegIdx(i)] = inst;
|
|
++freed_regs;
|
|
}
|
|
|
|
#if FULL_SYSTEM
|
|
if (thread->profile) {
|
|
// bool usermode =
|
|
// (xc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
|
|
// thread->profilePC = usermode ? 1 : inst->readPC();
|
|
thread->profilePC = inst->readPC();
|
|
ProfileNode *node = thread->profile->consume(thread->getTC(),
|
|
inst->staticInst);
|
|
|
|
if (node)
|
|
thread->profileNode = node;
|
|
}
|
|
#endif
|
|
|
|
if (inst->traceData) {
|
|
inst->traceData->setFetchSeq(inst->seqNum);
|
|
inst->traceData->setCPSeq(thread->numInst);
|
|
inst->traceData->finalize();
|
|
inst->traceData = NULL;
|
|
}
|
|
|
|
inst->clearDependents();
|
|
|
|
frontEnd->addFreeRegs(freed_regs);
|
|
|
|
instList.pop_back();
|
|
|
|
--numInsts;
|
|
++thread->funcExeInst;
|
|
// Maybe move this to where the fault is handled; if the fault is
|
|
// handled, don't try to set this myself as the fault will set it.
|
|
// If not, then I set thread->PC = thread->nextPC and
|
|
// thread->nextPC = thread->nextPC + 4.
|
|
thread->setPC(thread->readNextPC());
|
|
thread->setNextPC(thread->readNextPC() + sizeof(TheISA::MachInst));
|
|
updateComInstStats(inst);
|
|
|
|
// Write the done sequence number here.
|
|
toIEW->doneSeqNum = inst->seqNum;
|
|
lastCommitCycle = curTick();
|
|
|
|
#if FULL_SYSTEM
|
|
int count = 0;
|
|
Addr oldpc;
|
|
do {
|
|
if (count == 0)
|
|
assert(!thread->inSyscall && !thread->trapPending);
|
|
oldpc = thread->readPC();
|
|
cpu->system->pcEventQueue.service(
|
|
thread->getTC());
|
|
count++;
|
|
} while (oldpc != thread->readPC());
|
|
if (count > 1) {
|
|
DPRINTF(BE, "PC skip function event, stopping commit\n");
|
|
tcSquash = true;
|
|
return false;
|
|
}
|
|
#endif
|
|
return true;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::commitInsts()
|
|
{
|
|
// Not sure this should be a loop or not.
|
|
int inst_num = 0;
|
|
while (!instList.empty() && inst_num < commitWidth) {
|
|
if (instList.back()->isSquashed()) {
|
|
instList.back()->clearDependents();
|
|
ROBSquashedInsts[instList.back()->threadNumber]++;
|
|
instList.pop_back();
|
|
--numInsts;
|
|
continue;
|
|
}
|
|
|
|
if (!commitInst(inst_num++)) {
|
|
DPRINTF(BE, "Can't commit, Instruction [sn:%lli] PC "
|
|
"%#x is head of ROB and not ready\n",
|
|
instList.back()->seqNum, instList.back()->readPC());
|
|
--inst_num;
|
|
break;
|
|
}
|
|
}
|
|
nCommittedDist.sample(inst_num);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::squash(const InstSeqNum &sn)
|
|
{
|
|
LSQ.squash(sn);
|
|
|
|
int freed_regs = 0;
|
|
InstListIt insts_end_it = waitingList.end();
|
|
InstListIt insts_it = waitingList.begin();
|
|
|
|
while (insts_it != insts_end_it && (*insts_it)->seqNum > sn)
|
|
{
|
|
if ((*insts_it)->isSquashed()) {
|
|
++insts_it;
|
|
continue;
|
|
}
|
|
DPRINTF(BE, "Squashing instruction on waitingList PC %#x, [sn:%lli].\n",
|
|
(*insts_it)->readPC(),
|
|
(*insts_it)->seqNum);
|
|
|
|
if ((*insts_it)->isMemRef()) {
|
|
DPRINTF(BE, "Squashing a waiting mem op [sn:%lli]\n",
|
|
(*insts_it)->seqNum);
|
|
removeWaitingMemOp((*insts_it));
|
|
}
|
|
|
|
waitingList.erase(insts_it++);
|
|
waitingInsts--;
|
|
}
|
|
assert(waitingInsts >= 0);
|
|
|
|
insts_it = instList.begin();
|
|
|
|
while (!instList.empty() && (*insts_it)->seqNum > sn)
|
|
{
|
|
if ((*insts_it)->isSquashed()) {
|
|
panic("Instruction should not be already squashed and on list!");
|
|
++insts_it;
|
|
continue;
|
|
}
|
|
DPRINTF(BE, "Squashing instruction on inst list PC %#x, [sn:%lli].\n",
|
|
(*insts_it)->readPC(),
|
|
(*insts_it)->seqNum);
|
|
|
|
// Mark the instruction as squashed, and ready to commit so that
|
|
// it can drain out of the pipeline.
|
|
(*insts_it)->setSquashed();
|
|
|
|
(*insts_it)->setCanCommit();
|
|
|
|
(*insts_it)->clearInROB();
|
|
|
|
for (int i = 0; i < (*insts_it)->numDestRegs(); ++i) {
|
|
DynInstPtr prev_dest = (*insts_it)->getPrevDestInst(i);
|
|
DPRINTF(BE, "Commit rename map setting reg %i to [sn:%lli]\n",
|
|
(int)(*insts_it)->destRegIdx(i), prev_dest->seqNum);
|
|
renameTable[(*insts_it)->destRegIdx(i)] = prev_dest;
|
|
++freed_regs;
|
|
}
|
|
|
|
(*insts_it)->clearDependents();
|
|
|
|
squashedInsts[(*insts_it)->threadNumber]++;
|
|
|
|
instList.erase(insts_it++);
|
|
--numInsts;
|
|
}
|
|
|
|
while (memBarrier && memBarrier->seqNum > sn) {
|
|
DPRINTF(BE, "[sn:%lli] Memory barrier squashed (or previously "
|
|
"squashed)\n", memBarrier->seqNum);
|
|
memBarrier->clearMemDependents();
|
|
if (memBarrier->memDepReady()) {
|
|
DPRINTF(BE, "No previous barrier\n");
|
|
memBarrier = NULL;
|
|
} else {
|
|
std::list<DynInstPtr> &srcs = memBarrier->getMemSrcs();
|
|
memBarrier = srcs.front();
|
|
srcs.pop_front();
|
|
assert(srcs.empty());
|
|
DPRINTF(BE, "Previous barrier: [sn:%lli]\n",
|
|
memBarrier->seqNum);
|
|
}
|
|
}
|
|
|
|
insts_it = replayList.begin();
|
|
insts_end_it = replayList.end();
|
|
while (!replayList.empty() && insts_it != insts_end_it) {
|
|
if ((*insts_it)->seqNum < sn) {
|
|
++insts_it;
|
|
continue;
|
|
}
|
|
assert((*insts_it)->isSquashed());
|
|
|
|
replayList.erase(insts_it++);
|
|
}
|
|
|
|
frontEnd->addFreeRegs(freed_regs);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::squashFromTC()
|
|
{
|
|
InstSeqNum squashed_inst = robEmpty() ? 0 : instList.back()->seqNum - 1;
|
|
squash(squashed_inst);
|
|
frontEnd->squash(squashed_inst, thread->readPC(),
|
|
false, false);
|
|
frontEnd->interruptPending = false;
|
|
|
|
thread->trapPending = false;
|
|
thread->inSyscall = false;
|
|
tcSquash = false;
|
|
commitStatus = Running;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::squashFromTrap()
|
|
{
|
|
InstSeqNum squashed_inst = robEmpty() ? 0 : instList.back()->seqNum - 1;
|
|
squash(squashed_inst);
|
|
frontEnd->squash(squashed_inst, thread->readPC(),
|
|
false, false);
|
|
frontEnd->interruptPending = false;
|
|
|
|
thread->trapPending = false;
|
|
thread->inSyscall = false;
|
|
trapSquash = false;
|
|
commitStatus = Running;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::squashDueToBranch(DynInstPtr &inst)
|
|
{
|
|
// Update the branch predictor state I guess
|
|
DPRINTF(BE, "Squashing due to branch [sn:%lli], will restart at PC %#x\n",
|
|
inst->seqNum, inst->readNextPC());
|
|
squash(inst->seqNum);
|
|
frontEnd->squash(inst->seqNum, inst->readNextPC(),
|
|
true, inst->mispredicted());
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::squashDueToMemViolation(DynInstPtr &inst)
|
|
{
|
|
// Update the branch predictor state I guess
|
|
DPRINTF(BE, "Squashing due to violation [sn:%lli], will restart at PC %#x\n",
|
|
inst->seqNum, inst->readNextPC());
|
|
squash(inst->seqNum);
|
|
frontEnd->squash(inst->seqNum, inst->readNextPC(),
|
|
false, inst->mispredicted());
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::squashDueToMemBlocked(DynInstPtr &inst)
|
|
{
|
|
DPRINTF(IEW, "Memory blocked, squashing load and younger insts, "
|
|
"PC: %#x [sn:%i].\n", inst->readPC(), inst->seqNum);
|
|
|
|
squash(inst->seqNum - 1);
|
|
frontEnd->squash(inst->seqNum - 1, inst->readPC());
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::switchOut()
|
|
{
|
|
switchPending = true;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::doSwitchOut()
|
|
{
|
|
switchedOut = true;
|
|
switchPending = false;
|
|
// Need to get rid of all committed, non-speculative state and write it
|
|
// to memory/TC. In this case this is stores that have committed and not
|
|
// yet written back.
|
|
assert(robEmpty());
|
|
assert(!LSQ.hasStoresToWB());
|
|
writeback.clear();
|
|
for (int i = 0; i < numInstsToWB.getSize() + 1; ++i)
|
|
numInstsToWB.advance();
|
|
|
|
// squash(0);
|
|
assert(waitingList.empty());
|
|
assert(instList.empty());
|
|
assert(replayList.empty());
|
|
assert(writeback.empty());
|
|
LSQ.switchOut();
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::takeOverFrom(ThreadContext *old_tc)
|
|
{
|
|
assert(!squashPending);
|
|
squashSeqNum = 0;
|
|
squashNextPC = 0;
|
|
tcSquash = false;
|
|
trapSquash = false;
|
|
|
|
numInsts = 0;
|
|
numWaitingMemOps = 0;
|
|
waitingMemOps.clear();
|
|
waitingInsts = 0;
|
|
switchedOut = false;
|
|
dispatchStatus = Running;
|
|
commitStatus = Running;
|
|
LSQ.takeOverFrom(old_tc);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::updateExeInstStats(DynInstPtr &inst)
|
|
{
|
|
ThreadID tid = inst->threadNumber;
|
|
|
|
//
|
|
// Pick off the software prefetches
|
|
//
|
|
#ifdef TARGET_ALPHA
|
|
if (inst->isDataPrefetch())
|
|
exeSwp[tid]++;
|
|
else
|
|
exeInst[tid]++;
|
|
#else
|
|
exeInst[tid]++;
|
|
#endif
|
|
|
|
//
|
|
// Control operations
|
|
//
|
|
if (inst->isControl())
|
|
exeBranches[tid]++;
|
|
|
|
//
|
|
// Memory operations
|
|
//
|
|
if (inst->isMemRef()) {
|
|
exeRefs[tid]++;
|
|
|
|
if (inst->isLoad())
|
|
exeLoads[tid]++;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::updateComInstStats(DynInstPtr &inst)
|
|
{
|
|
ThreadID tid = inst->threadNumber;
|
|
|
|
// keep an instruction count
|
|
thread->numInst++;
|
|
thread->numInsts++;
|
|
|
|
cpu->numInst++;
|
|
//
|
|
// Pick off the software prefetches
|
|
//
|
|
#ifdef TARGET_ALPHA
|
|
if (inst->isDataPrefetch()) {
|
|
statComSwp[tid]++;
|
|
} else {
|
|
statComInst[tid]++;
|
|
}
|
|
#else
|
|
statComInst[tid]++;
|
|
#endif
|
|
|
|
//
|
|
// Control Instructions
|
|
//
|
|
if (inst->isControl())
|
|
statComBranches[tid]++;
|
|
|
|
//
|
|
// Memory references
|
|
//
|
|
if (inst->isMemRef()) {
|
|
statComRefs[tid]++;
|
|
|
|
if (inst->isLoad()) {
|
|
statComLoads[tid]++;
|
|
}
|
|
}
|
|
|
|
if (inst->isMemBarrier()) {
|
|
statComMembars[tid]++;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LWBackEnd<Impl>::dumpInsts()
|
|
{
|
|
int num = 0;
|
|
int valid_num = 0;
|
|
|
|
InstListIt inst_list_it = --(instList.end());
|
|
|
|
cprintf("ExeList size: %i\n", exeList.size());
|
|
|
|
cprintf("Inst list size: %i\n", instList.size());
|
|
|
|
while (inst_list_it != instList.end())
|
|
{
|
|
cprintf("Instruction:%i\n",
|
|
num);
|
|
if (!(*inst_list_it)->isSquashed()) {
|
|
if (!(*inst_list_it)->isIssued()) {
|
|
++valid_num;
|
|
cprintf("Count:%i\n", valid_num);
|
|
} else if ((*inst_list_it)->isMemRef() &&
|
|
!(*inst_list_it)->memOpDone) {
|
|
// Loads that have not been marked as executed still count
|
|
// towards the total instructions.
|
|
++valid_num;
|
|
cprintf("Count:%i\n", valid_num);
|
|
}
|
|
}
|
|
|
|
cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
|
|
"Issued:%i\nSquashed:%i\n",
|
|
(*inst_list_it)->readPC(),
|
|
(*inst_list_it)->seqNum,
|
|
(*inst_list_it)->threadNumber,
|
|
(*inst_list_it)->isIssued(),
|
|
(*inst_list_it)->isSquashed());
|
|
|
|
if ((*inst_list_it)->isMemRef()) {
|
|
cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
|
|
}
|
|
|
|
cprintf("\n");
|
|
|
|
inst_list_it--;
|
|
++num;
|
|
}
|
|
|
|
inst_list_it = --(writeback.end());
|
|
|
|
cprintf("Writeback list size: %i\n", writeback.size());
|
|
|
|
while (inst_list_it != writeback.end())
|
|
{
|
|
cprintf("Instruction:%i\n",
|
|
num);
|
|
if (!(*inst_list_it)->isSquashed()) {
|
|
if (!(*inst_list_it)->isIssued()) {
|
|
++valid_num;
|
|
cprintf("Count:%i\n", valid_num);
|
|
} else if ((*inst_list_it)->isMemRef() &&
|
|
!(*inst_list_it)->memOpDone) {
|
|
// Loads that have not been marked as executed still count
|
|
// towards the total instructions.
|
|
++valid_num;
|
|
cprintf("Count:%i\n", valid_num);
|
|
}
|
|
}
|
|
|
|
cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
|
|
"Issued:%i\nSquashed:%i\n",
|
|
(*inst_list_it)->readPC(),
|
|
(*inst_list_it)->seqNum,
|
|
(*inst_list_it)->threadNumber,
|
|
(*inst_list_it)->isIssued(),
|
|
(*inst_list_it)->isSquashed());
|
|
|
|
if ((*inst_list_it)->isMemRef()) {
|
|
cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
|
|
}
|
|
|
|
cprintf("\n");
|
|
|
|
inst_list_it--;
|
|
++num;
|
|
}
|
|
|
|
cprintf("Waiting list size: %i\n", waitingList.size());
|
|
|
|
inst_list_it = --(waitingList.end());
|
|
|
|
while (inst_list_it != waitingList.end())
|
|
{
|
|
cprintf("Instruction:%i\n",
|
|
num);
|
|
if (!(*inst_list_it)->isSquashed()) {
|
|
if (!(*inst_list_it)->isIssued()) {
|
|
++valid_num;
|
|
cprintf("Count:%i\n", valid_num);
|
|
} else if ((*inst_list_it)->isMemRef() &&
|
|
!(*inst_list_it)->memOpDone) {
|
|
// Loads that have not been marked as executed still count
|
|
// towards the total instructions.
|
|
++valid_num;
|
|
cprintf("Count:%i\n", valid_num);
|
|
}
|
|
}
|
|
|
|
cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
|
|
"Issued:%i\nSquashed:%i\n",
|
|
(*inst_list_it)->readPC(),
|
|
(*inst_list_it)->seqNum,
|
|
(*inst_list_it)->threadNumber,
|
|
(*inst_list_it)->isIssued(),
|
|
(*inst_list_it)->isSquashed());
|
|
|
|
if ((*inst_list_it)->isMemRef()) {
|
|
cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
|
|
}
|
|
|
|
cprintf("\n");
|
|
|
|
inst_list_it--;
|
|
++num;
|
|
}
|
|
|
|
cprintf("waitingMemOps list size: %i\n", waitingMemOps.size());
|
|
|
|
MemIt waiting_it = waitingMemOps.begin();
|
|
|
|
while (waiting_it != waitingMemOps.end())
|
|
{
|
|
cprintf("[sn:%lli] ", (*waiting_it));
|
|
waiting_it++;
|
|
++num;
|
|
}
|
|
cprintf("\n");
|
|
}
|