eddac53ff6
At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
1483 lines
43 KiB
C++
1483 lines
43 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Korey Sewell
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*/
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#include <algorithm>
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#include <cstring>
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#include "arch/isa_traits.hh"
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#include "arch/utility.hh"
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#include "base/types.hh"
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#include "config/the_isa.hh"
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#include "config/use_checker.hh"
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#include "cpu/checker/cpu.hh"
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#include "cpu/o3/fetch.hh"
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#include "cpu/exetrace.hh"
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#include "debug/Activity.hh"
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#include "debug/Fetch.hh"
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#include "mem/packet.hh"
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#include "mem/request.hh"
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#include "params/DerivO3CPU.hh"
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#include "sim/byteswap.hh"
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#include "sim/core.hh"
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#if FULL_SYSTEM
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#include "arch/tlb.hh"
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#include "arch/vtophys.hh"
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#include "sim/system.hh"
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#endif // FULL_SYSTEM
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using namespace std;
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template<class Impl>
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void
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DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
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{
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Port::setPeer(port);
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fetch->setIcache();
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}
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template<class Impl>
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Tick
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DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
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{
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panic("DefaultFetch doesn't expect recvAtomic callback!");
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return curTick();
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}
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template<class Impl>
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void
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DefaultFetch<Impl>::IcachePort::recvFunctional(PacketPtr pkt)
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{
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DPRINTF(Fetch, "DefaultFetch doesn't update its state from a "
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"functional call.");
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}
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template<class Impl>
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void
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DefaultFetch<Impl>::IcachePort::recvStatusChange(Status status)
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{
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if (status == RangeChange) {
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if (!snoopRangeSent) {
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snoopRangeSent = true;
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sendStatusChange(Port::RangeChange);
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}
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return;
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}
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panic("DefaultFetch doesn't expect recvStatusChange callback!");
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}
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template<class Impl>
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bool
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DefaultFetch<Impl>::IcachePort::recvTiming(PacketPtr pkt)
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{
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DPRINTF(Fetch, "Received timing\n");
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if (pkt->isResponse()) {
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// We shouldn't ever get a block in ownership state
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assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
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fetch->processCacheCompletion(pkt);
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}
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//else Snooped a coherence request, just return
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return true;
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}
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template<class Impl>
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void
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DefaultFetch<Impl>::IcachePort::recvRetry()
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{
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fetch->recvRetry();
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}
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template<class Impl>
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DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
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: cpu(_cpu),
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branchPred(params),
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predecoder(NULL),
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decodeToFetchDelay(params->decodeToFetchDelay),
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renameToFetchDelay(params->renameToFetchDelay),
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iewToFetchDelay(params->iewToFetchDelay),
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commitToFetchDelay(params->commitToFetchDelay),
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fetchWidth(params->fetchWidth),
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cacheBlocked(false),
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retryPkt(NULL),
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retryTid(InvalidThreadID),
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numThreads(params->numThreads),
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numFetchingThreads(params->smtNumFetchingThreads),
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interruptPending(false),
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drainPending(false),
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switchedOut(false)
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{
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if (numThreads > Impl::MaxThreads)
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fatal("numThreads (%d) is larger than compiled limit (%d),\n"
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"\tincrease MaxThreads in src/cpu/o3/impl.hh\n",
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numThreads, static_cast<int>(Impl::MaxThreads));
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// Set fetch stage's status to inactive.
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_status = Inactive;
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std::string policy = params->smtFetchPolicy;
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// Convert string to lowercase
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std::transform(policy.begin(), policy.end(), policy.begin(),
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(int(*)(int)) tolower);
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// Figure out fetch policy
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if (policy == "singlethread") {
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fetchPolicy = SingleThread;
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if (numThreads > 1)
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panic("Invalid Fetch Policy for a SMT workload.");
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} else if (policy == "roundrobin") {
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fetchPolicy = RoundRobin;
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DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
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} else if (policy == "branch") {
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fetchPolicy = Branch;
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DPRINTF(Fetch, "Fetch policy set to Branch Count\n");
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} else if (policy == "iqcount") {
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fetchPolicy = IQ;
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DPRINTF(Fetch, "Fetch policy set to IQ count\n");
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} else if (policy == "lsqcount") {
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fetchPolicy = LSQ;
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DPRINTF(Fetch, "Fetch policy set to LSQ count\n");
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} else {
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fatal("Invalid Fetch Policy. Options Are: {SingleThread,"
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" RoundRobin,LSQcount,IQcount}\n");
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}
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// Get the size of an instruction.
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instSize = sizeof(TheISA::MachInst);
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// Name is finally available, so create the port.
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icachePort = new IcachePort(this);
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icachePort->snoopRangeSent = false;
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#if USE_CHECKER
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if (cpu->checker) {
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cpu->checker->setIcachePort(icachePort);
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}
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#endif
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}
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template <class Impl>
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std::string
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DefaultFetch<Impl>::name() const
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{
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return cpu->name() + ".fetch";
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}
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template <class Impl>
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void
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DefaultFetch<Impl>::regStats()
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{
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icacheStallCycles
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.name(name() + ".icacheStallCycles")
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.desc("Number of cycles fetch is stalled on an Icache miss")
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.prereq(icacheStallCycles);
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fetchedInsts
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.name(name() + ".Insts")
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.desc("Number of instructions fetch has processed")
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.prereq(fetchedInsts);
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fetchedBranches
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.name(name() + ".Branches")
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.desc("Number of branches that fetch encountered")
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.prereq(fetchedBranches);
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predictedBranches
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.name(name() + ".predictedBranches")
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.desc("Number of branches that fetch has predicted taken")
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.prereq(predictedBranches);
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fetchCycles
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.name(name() + ".Cycles")
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.desc("Number of cycles fetch has run and was not squashing or"
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" blocked")
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.prereq(fetchCycles);
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fetchSquashCycles
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.name(name() + ".SquashCycles")
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.desc("Number of cycles fetch has spent squashing")
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.prereq(fetchSquashCycles);
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fetchTlbCycles
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.name(name() + ".TlbCycles")
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.desc("Number of cycles fetch has spent waiting for tlb")
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.prereq(fetchTlbCycles);
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fetchIdleCycles
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.name(name() + ".IdleCycles")
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.desc("Number of cycles fetch was idle")
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.prereq(fetchIdleCycles);
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fetchBlockedCycles
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.name(name() + ".BlockedCycles")
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.desc("Number of cycles fetch has spent blocked")
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.prereq(fetchBlockedCycles);
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fetchedCacheLines
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.name(name() + ".CacheLines")
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.desc("Number of cache lines fetched")
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.prereq(fetchedCacheLines);
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fetchMiscStallCycles
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.name(name() + ".MiscStallCycles")
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.desc("Number of cycles fetch has spent waiting on interrupts, or "
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"bad addresses, or out of MSHRs")
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.prereq(fetchMiscStallCycles);
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fetchIcacheSquashes
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.name(name() + ".IcacheSquashes")
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.desc("Number of outstanding Icache misses that were squashed")
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.prereq(fetchIcacheSquashes);
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fetchTlbSquashes
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.name(name() + ".ItlbSquashes")
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.desc("Number of outstanding ITLB misses that were squashed")
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.prereq(fetchTlbSquashes);
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fetchNisnDist
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.init(/* base value */ 0,
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/* last value */ fetchWidth,
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/* bucket size */ 1)
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.name(name() + ".rateDist")
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.desc("Number of instructions fetched each cycle (Total)")
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.flags(Stats::pdf);
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idleRate
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.name(name() + ".idleRate")
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.desc("Percent of cycles fetch was idle")
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.prereq(idleRate);
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idleRate = fetchIdleCycles * 100 / cpu->numCycles;
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branchRate
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.name(name() + ".branchRate")
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.desc("Number of branch fetches per cycle")
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.flags(Stats::total);
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branchRate = fetchedBranches / cpu->numCycles;
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fetchRate
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.name(name() + ".rate")
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.desc("Number of inst fetches per cycle")
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.flags(Stats::total);
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fetchRate = fetchedInsts / cpu->numCycles;
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branchPred.regStats();
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}
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template<class Impl>
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void
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DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
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{
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timeBuffer = time_buffer;
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// Create wires to get information from proper places in time buffer.
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fromDecode = timeBuffer->getWire(-decodeToFetchDelay);
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fromRename = timeBuffer->getWire(-renameToFetchDelay);
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fromIEW = timeBuffer->getWire(-iewToFetchDelay);
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fromCommit = timeBuffer->getWire(-commitToFetchDelay);
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}
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template<class Impl>
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void
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DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
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{
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activeThreads = at_ptr;
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}
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template<class Impl>
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void
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DefaultFetch<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
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{
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fetchQueue = fq_ptr;
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// Create wire to write information to proper place in fetch queue.
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toDecode = fetchQueue->getWire(0);
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}
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template<class Impl>
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void
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DefaultFetch<Impl>::initStage()
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{
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// Setup PC and nextPC with initial state.
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for (ThreadID tid = 0; tid < numThreads; tid++) {
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pc[tid] = cpu->pcState(tid);
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fetchOffset[tid] = 0;
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macroop[tid] = NULL;
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}
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for (ThreadID tid = 0; tid < numThreads; tid++) {
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fetchStatus[tid] = Running;
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priorityList.push_back(tid);
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memReq[tid] = NULL;
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stalls[tid].decode = false;
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stalls[tid].rename = false;
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stalls[tid].iew = false;
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stalls[tid].commit = false;
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}
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// Schedule fetch to get the correct PC from the CPU
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// scheduleFetchStartupEvent(1);
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// Fetch needs to start fetching instructions at the very beginning,
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// so it must start up in active state.
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switchToActive();
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}
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template<class Impl>
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void
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DefaultFetch<Impl>::setIcache()
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{
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// Size of cache block.
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cacheBlkSize = icachePort->peerBlockSize();
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// Create mask to get rid of offset bits.
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cacheBlkMask = (cacheBlkSize - 1);
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for (ThreadID tid = 0; tid < numThreads; tid++) {
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// Create space to store a cache line.
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cacheData[tid] = new uint8_t[cacheBlkSize];
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cacheDataPC[tid] = 0;
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cacheDataValid[tid] = false;
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}
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}
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template<class Impl>
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void
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DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
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{
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ThreadID tid = pkt->req->threadId();
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DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid);
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assert(!pkt->wasNacked());
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// Only change the status if it's still waiting on the icache access
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// to return.
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if (fetchStatus[tid] != IcacheWaitResponse ||
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pkt->req != memReq[tid] ||
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isSwitchedOut()) {
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++fetchIcacheSquashes;
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delete pkt->req;
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delete pkt;
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return;
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}
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memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
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cacheDataValid[tid] = true;
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if (!drainPending) {
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// Wake up the CPU (if it went to sleep and was waiting on
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// this completion event).
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cpu->wakeCPU();
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DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n",
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tid);
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switchToActive();
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}
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// Only switch to IcacheAccessComplete if we're not stalled as well.
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if (checkStall(tid)) {
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fetchStatus[tid] = Blocked;
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} else {
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fetchStatus[tid] = IcacheAccessComplete;
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}
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// Reset the mem req to NULL.
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delete pkt->req;
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delete pkt;
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memReq[tid] = NULL;
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}
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template <class Impl>
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bool
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DefaultFetch<Impl>::drain()
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{
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// Fetch is ready to drain at any time.
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cpu->signalDrained();
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drainPending = true;
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return true;
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}
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|
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template <class Impl>
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void
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DefaultFetch<Impl>::resume()
|
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{
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drainPending = false;
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}
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|
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template <class Impl>
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void
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DefaultFetch<Impl>::switchOut()
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{
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switchedOut = true;
|
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// Branch predictor needs to have its state cleared.
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branchPred.switchOut();
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}
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template <class Impl>
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void
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DefaultFetch<Impl>::takeOverFrom()
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{
|
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// Reset all state
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for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
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stalls[i].decode = 0;
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stalls[i].rename = 0;
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stalls[i].iew = 0;
|
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stalls[i].commit = 0;
|
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pc[i] = cpu->pcState(i);
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fetchStatus[i] = Running;
|
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}
|
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numInst = 0;
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|
wroteToTimeBuffer = false;
|
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_status = Inactive;
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switchedOut = false;
|
|
interruptPending = false;
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branchPred.takeOverFrom();
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}
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|
|
|
template <class Impl>
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|
void
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DefaultFetch<Impl>::wakeFromQuiesce()
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|
{
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DPRINTF(Fetch, "Waking up from quiesce\n");
|
|
// Hopefully this is safe
|
|
// @todo: Allow other threads to wake from quiesce.
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fetchStatus[0] = Running;
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|
}
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|
|
template <class Impl>
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|
inline void
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|
DefaultFetch<Impl>::switchToActive()
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|
{
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if (_status == Inactive) {
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DPRINTF(Activity, "Activating stage.\n");
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|
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|
cpu->activateStage(O3CPU::FetchIdx);
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|
_status = Active;
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|
}
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|
}
|
|
|
|
template <class Impl>
|
|
inline void
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|
DefaultFetch<Impl>::switchToInactive()
|
|
{
|
|
if (_status == Active) {
|
|
DPRINTF(Activity, "Deactivating stage.\n");
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|
cpu->deactivateStage(O3CPU::FetchIdx);
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|
_status = Inactive;
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}
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|
}
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|
|
template <class Impl>
|
|
bool
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|
DefaultFetch<Impl>::lookupAndUpdateNextPC(
|
|
DynInstPtr &inst, TheISA::PCState &nextPC)
|
|
{
|
|
// Do branch prediction check here.
|
|
// A bit of a misnomer...next_PC is actually the current PC until
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|
// this function updates it.
|
|
bool predict_taken;
|
|
|
|
if (!inst->isControl()) {
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|
TheISA::advancePC(nextPC, inst->staticInst);
|
|
inst->setPredTarg(nextPC);
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|
inst->setPredTaken(false);
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|
return false;
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|
}
|
|
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|
ThreadID tid = inst->threadNumber;
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|
predict_taken = branchPred.predict(inst, nextPC, tid);
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|
|
|
if (predict_taken) {
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|
DPRINTF(Fetch, "[tid:%i]: [sn:%i]: Branch predicted to be taken to %s.\n",
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|
tid, inst->seqNum, nextPC);
|
|
} else {
|
|
DPRINTF(Fetch, "[tid:%i]: [sn:%i]:Branch predicted to be not taken.\n",
|
|
tid, inst->seqNum);
|
|
}
|
|
|
|
DPRINTF(Fetch, "[tid:%i]: [sn:%i] Branch predicted to go to %s.\n",
|
|
tid, inst->seqNum, nextPC);
|
|
inst->setPredTarg(nextPC);
|
|
inst->setPredTaken(predict_taken);
|
|
|
|
++fetchedBranches;
|
|
|
|
if (predict_taken) {
|
|
++predictedBranches;
|
|
}
|
|
|
|
return predict_taken;
|
|
}
|
|
|
|
template <class Impl>
|
|
bool
|
|
DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
|
|
{
|
|
Fault fault = NoFault;
|
|
|
|
// @todo: not sure if these should block translation.
|
|
//AlphaDep
|
|
if (cacheBlocked) {
|
|
DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
|
|
tid);
|
|
return false;
|
|
} else if (isSwitchedOut()) {
|
|
DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, switched out\n",
|
|
tid);
|
|
return false;
|
|
} else if (checkInterrupt(pc)) {
|
|
// Hold off fetch from getting new instructions when:
|
|
// Cache is blocked, or
|
|
// while an interrupt is pending and we're not in PAL mode, or
|
|
// fetch is switched out.
|
|
DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
|
|
tid);
|
|
return false;
|
|
}
|
|
|
|
// Align the fetch address so it's at the start of a cache block.
|
|
Addr block_PC = icacheBlockAlignPC(vaddr);
|
|
|
|
DPRINTF(Fetch, "[tid:%i] Fetching cache line %#x for addr %#x\n",
|
|
tid, block_PC, vaddr);
|
|
|
|
// Setup the memReq to do a read of the first instruction's address.
|
|
// Set the appropriate read size and flags as well.
|
|
// Build request here.
|
|
RequestPtr mem_req =
|
|
new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
|
|
pc, cpu->thread[tid]->contextId(), tid);
|
|
|
|
memReq[tid] = mem_req;
|
|
|
|
// Initiate translation of the icache block
|
|
fetchStatus[tid] = ItlbWait;
|
|
FetchTranslation *trans = new FetchTranslation(this);
|
|
cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(),
|
|
trans, BaseTLB::Execute);
|
|
return true;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
|
|
{
|
|
ThreadID tid = mem_req->threadId();
|
|
Addr block_PC = mem_req->getVaddr();
|
|
|
|
// Wake up CPU if it was idle
|
|
cpu->wakeCPU();
|
|
|
|
if (fetchStatus[tid] != ItlbWait || mem_req != memReq[tid] ||
|
|
mem_req->getVaddr() != memReq[tid]->getVaddr() || isSwitchedOut()) {
|
|
DPRINTF(Fetch, "[tid:%i] Ignoring itlb completed after squash\n",
|
|
tid);
|
|
++fetchTlbSquashes;
|
|
delete mem_req;
|
|
return;
|
|
}
|
|
|
|
|
|
// If translation was successful, attempt to read the icache block.
|
|
if (fault == NoFault) {
|
|
// Build packet here.
|
|
PacketPtr data_pkt = new Packet(mem_req,
|
|
MemCmd::ReadReq, Packet::Broadcast);
|
|
data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
|
|
|
|
cacheDataPC[tid] = block_PC;
|
|
cacheDataValid[tid] = false;
|
|
DPRINTF(Fetch, "Fetch: Doing instruction read.\n");
|
|
|
|
fetchedCacheLines++;
|
|
|
|
// Access the cache.
|
|
if (!icachePort->sendTiming(data_pkt)) {
|
|
assert(retryPkt == NULL);
|
|
assert(retryTid == InvalidThreadID);
|
|
DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
|
|
|
|
fetchStatus[tid] = IcacheWaitRetry;
|
|
retryPkt = data_pkt;
|
|
retryTid = tid;
|
|
cacheBlocked = true;
|
|
} else {
|
|
DPRINTF(Fetch, "[tid:%i]: Doing Icache access.\n", tid);
|
|
DPRINTF(Activity, "[tid:%i]: Activity: Waiting on I-cache "
|
|
"response.\n", tid);
|
|
|
|
lastIcacheStall[tid] = curTick();
|
|
fetchStatus[tid] = IcacheWaitResponse;
|
|
}
|
|
} else {
|
|
DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n",
|
|
mem_req->getVaddr(), memReq[tid]->getVaddr());
|
|
// Translation faulted, icache request won't be sent.
|
|
delete mem_req;
|
|
memReq[tid] = NULL;
|
|
|
|
// Send the fault to commit. This thread will not do anything
|
|
// until commit handles the fault. The only other way it can
|
|
// wake up is if a squash comes along and changes the PC.
|
|
TheISA::PCState fetchPC = pc[tid];
|
|
|
|
DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid);
|
|
// We will use a nop in ordier to carry the fault.
|
|
DynInstPtr instruction = buildInst(tid,
|
|
StaticInstPtr(TheISA::NoopMachInst, fetchPC.instAddr()),
|
|
NULL, fetchPC, fetchPC, false);
|
|
|
|
instruction->setPredTarg(fetchPC);
|
|
instruction->fault = fault;
|
|
wroteToTimeBuffer = true;
|
|
|
|
DPRINTF(Activity, "Activity this cycle.\n");
|
|
cpu->activityThisCycle();
|
|
|
|
fetchStatus[tid] = TrapPending;
|
|
|
|
DPRINTF(Fetch, "[tid:%i]: Blocked, need to handle the trap.\n", tid);
|
|
DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %s.\n",
|
|
tid, fault->name(), pc[tid]);
|
|
}
|
|
_status = updateFetchStatus();
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC, ThreadID tid)
|
|
{
|
|
DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %s.\n",
|
|
tid, newPC);
|
|
|
|
pc[tid] = newPC;
|
|
fetchOffset[tid] = 0;
|
|
macroop[tid] = NULL;
|
|
predecoder.reset();
|
|
|
|
// Clear the icache miss if it's outstanding.
|
|
if (fetchStatus[tid] == IcacheWaitResponse) {
|
|
DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
|
|
tid);
|
|
memReq[tid] = NULL;
|
|
} else if (fetchStatus[tid] == ItlbWait) {
|
|
DPRINTF(Fetch, "[tid:%i]: Squashing outstanding ITLB miss.\n",
|
|
tid);
|
|
memReq[tid] = NULL;
|
|
}
|
|
|
|
// Get rid of the retrying packet if it was from this thread.
|
|
if (retryTid == tid) {
|
|
assert(cacheBlocked);
|
|
if (retryPkt) {
|
|
delete retryPkt->req;
|
|
delete retryPkt;
|
|
}
|
|
retryPkt = NULL;
|
|
retryTid = InvalidThreadID;
|
|
}
|
|
|
|
fetchStatus[tid] = Squashing;
|
|
|
|
++fetchSquashCycles;
|
|
}
|
|
|
|
template<class Impl>
|
|
void
|
|
DefaultFetch<Impl>::squashFromDecode(const TheISA::PCState &newPC,
|
|
const InstSeqNum &seq_num, ThreadID tid)
|
|
{
|
|
DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n", tid);
|
|
|
|
doSquash(newPC, tid);
|
|
|
|
// Tell the CPU to remove any instructions that are in flight between
|
|
// fetch and decode.
|
|
cpu->removeInstsUntil(seq_num, tid);
|
|
}
|
|
|
|
template<class Impl>
|
|
bool
|
|
DefaultFetch<Impl>::checkStall(ThreadID tid) const
|
|
{
|
|
bool ret_val = false;
|
|
|
|
if (cpu->contextSwitch) {
|
|
DPRINTF(Fetch,"[tid:%i]: Stalling for a context switch.\n",tid);
|
|
ret_val = true;
|
|
} else if (stalls[tid].decode) {
|
|
DPRINTF(Fetch,"[tid:%i]: Stall from Decode stage detected.\n",tid);
|
|
ret_val = true;
|
|
} else if (stalls[tid].rename) {
|
|
DPRINTF(Fetch,"[tid:%i]: Stall from Rename stage detected.\n",tid);
|
|
ret_val = true;
|
|
} else if (stalls[tid].iew) {
|
|
DPRINTF(Fetch,"[tid:%i]: Stall from IEW stage detected.\n",tid);
|
|
ret_val = true;
|
|
} else if (stalls[tid].commit) {
|
|
DPRINTF(Fetch,"[tid:%i]: Stall from Commit stage detected.\n",tid);
|
|
ret_val = true;
|
|
}
|
|
|
|
return ret_val;
|
|
}
|
|
|
|
template<class Impl>
|
|
typename DefaultFetch<Impl>::FetchStatus
|
|
DefaultFetch<Impl>::updateFetchStatus()
|
|
{
|
|
//Check Running
|
|
list<ThreadID>::iterator threads = activeThreads->begin();
|
|
list<ThreadID>::iterator end = activeThreads->end();
|
|
|
|
while (threads != end) {
|
|
ThreadID tid = *threads++;
|
|
|
|
if (fetchStatus[tid] == Running ||
|
|
fetchStatus[tid] == Squashing ||
|
|
fetchStatus[tid] == IcacheAccessComplete) {
|
|
|
|
if (_status == Inactive) {
|
|
DPRINTF(Activity, "[tid:%i]: Activating stage.\n",tid);
|
|
|
|
if (fetchStatus[tid] == IcacheAccessComplete) {
|
|
DPRINTF(Activity, "[tid:%i]: Activating fetch due to cache"
|
|
"completion\n",tid);
|
|
}
|
|
|
|
cpu->activateStage(O3CPU::FetchIdx);
|
|
}
|
|
|
|
return Active;
|
|
}
|
|
}
|
|
|
|
// Stage is switching from active to inactive, notify CPU of it.
|
|
if (_status == Active) {
|
|
DPRINTF(Activity, "Deactivating stage.\n");
|
|
|
|
cpu->deactivateStage(O3CPU::FetchIdx);
|
|
}
|
|
|
|
return Inactive;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
|
|
const InstSeqNum &seq_num, DynInstPtr &squashInst,
|
|
ThreadID tid)
|
|
{
|
|
DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
|
|
|
|
doSquash(newPC, tid);
|
|
|
|
// Tell the CPU to remove any instructions that are not in the ROB.
|
|
cpu->removeInstsNotInROB(tid);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
DefaultFetch<Impl>::tick()
|
|
{
|
|
list<ThreadID>::iterator threads = activeThreads->begin();
|
|
list<ThreadID>::iterator end = activeThreads->end();
|
|
bool status_change = false;
|
|
|
|
wroteToTimeBuffer = false;
|
|
|
|
while (threads != end) {
|
|
ThreadID tid = *threads++;
|
|
|
|
// Check the signals for each thread to determine the proper status
|
|
// for each thread.
|
|
bool updated_status = checkSignalsAndUpdate(tid);
|
|
status_change = status_change || updated_status;
|
|
}
|
|
|
|
DPRINTF(Fetch, "Running stage.\n");
|
|
|
|
// Reset the number of the instruction we're fetching.
|
|
numInst = 0;
|
|
|
|
#if FULL_SYSTEM
|
|
if (fromCommit->commitInfo[0].interruptPending) {
|
|
interruptPending = true;
|
|
}
|
|
|
|
if (fromCommit->commitInfo[0].clearInterrupt) {
|
|
interruptPending = false;
|
|
}
|
|
#endif
|
|
|
|
for (threadFetched = 0; threadFetched < numFetchingThreads;
|
|
threadFetched++) {
|
|
// Fetch each of the actively fetching threads.
|
|
fetch(status_change);
|
|
}
|
|
|
|
// Record number of instructions fetched this cycle for distribution.
|
|
fetchNisnDist.sample(numInst);
|
|
|
|
if (status_change) {
|
|
// Change the fetch stage status if there was a status change.
|
|
_status = updateFetchStatus();
|
|
}
|
|
|
|
// If there was activity this cycle, inform the CPU of it.
|
|
if (wroteToTimeBuffer || cpu->contextSwitch) {
|
|
DPRINTF(Activity, "Activity this cycle.\n");
|
|
|
|
cpu->activityThisCycle();
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
bool
|
|
DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
|
|
{
|
|
// Update the per thread stall statuses.
|
|
if (fromDecode->decodeBlock[tid]) {
|
|
stalls[tid].decode = true;
|
|
}
|
|
|
|
if (fromDecode->decodeUnblock[tid]) {
|
|
assert(stalls[tid].decode);
|
|
assert(!fromDecode->decodeBlock[tid]);
|
|
stalls[tid].decode = false;
|
|
}
|
|
|
|
if (fromRename->renameBlock[tid]) {
|
|
stalls[tid].rename = true;
|
|
}
|
|
|
|
if (fromRename->renameUnblock[tid]) {
|
|
assert(stalls[tid].rename);
|
|
assert(!fromRename->renameBlock[tid]);
|
|
stalls[tid].rename = false;
|
|
}
|
|
|
|
if (fromIEW->iewBlock[tid]) {
|
|
stalls[tid].iew = true;
|
|
}
|
|
|
|
if (fromIEW->iewUnblock[tid]) {
|
|
assert(stalls[tid].iew);
|
|
assert(!fromIEW->iewBlock[tid]);
|
|
stalls[tid].iew = false;
|
|
}
|
|
|
|
if (fromCommit->commitBlock[tid]) {
|
|
stalls[tid].commit = true;
|
|
}
|
|
|
|
if (fromCommit->commitUnblock[tid]) {
|
|
assert(stalls[tid].commit);
|
|
assert(!fromCommit->commitBlock[tid]);
|
|
stalls[tid].commit = false;
|
|
}
|
|
|
|
// Check squash signals from commit.
|
|
if (fromCommit->commitInfo[tid].squash) {
|
|
|
|
DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
|
|
"from commit.\n",tid);
|
|
// In any case, squash.
|
|
squash(fromCommit->commitInfo[tid].pc,
|
|
fromCommit->commitInfo[tid].doneSeqNum,
|
|
fromCommit->commitInfo[tid].squashInst, tid);
|
|
|
|
// If it was a branch mispredict on a control instruction, update the
|
|
// branch predictor with that instruction, otherwise just kill the
|
|
// invalid state we generated in after sequence number
|
|
if (fromCommit->commitInfo[tid].mispredictInst &&
|
|
fromCommit->commitInfo[tid].mispredictInst->isControl()) {
|
|
branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
|
|
fromCommit->commitInfo[tid].pc,
|
|
fromCommit->commitInfo[tid].branchTaken,
|
|
tid);
|
|
} else {
|
|
branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
|
|
tid);
|
|
}
|
|
|
|
return true;
|
|
} else if (fromCommit->commitInfo[tid].doneSeqNum) {
|
|
// Update the branch predictor if it wasn't a squashed instruction
|
|
// that was broadcasted.
|
|
branchPred.update(fromCommit->commitInfo[tid].doneSeqNum, tid);
|
|
}
|
|
|
|
// Check ROB squash signals from commit.
|
|
if (fromCommit->commitInfo[tid].robSquashing) {
|
|
DPRINTF(Fetch, "[tid:%u]: ROB is still squashing.\n", tid);
|
|
|
|
// Continue to squash.
|
|
fetchStatus[tid] = Squashing;
|
|
|
|
return true;
|
|
}
|
|
|
|
// Check squash signals from decode.
|
|
if (fromDecode->decodeInfo[tid].squash) {
|
|
DPRINTF(Fetch, "[tid:%u]: Squashing instructions due to squash "
|
|
"from decode.\n",tid);
|
|
|
|
// Update the branch predictor.
|
|
if (fromDecode->decodeInfo[tid].branchMispredict) {
|
|
branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
|
|
fromDecode->decodeInfo[tid].nextPC,
|
|
fromDecode->decodeInfo[tid].branchTaken,
|
|
tid);
|
|
} else {
|
|
branchPred.squash(fromDecode->decodeInfo[tid].doneSeqNum,
|
|
tid);
|
|
}
|
|
|
|
if (fetchStatus[tid] != Squashing) {
|
|
|
|
TheISA::PCState nextPC = fromDecode->decodeInfo[tid].nextPC;
|
|
DPRINTF(Fetch, "Squashing from decode with PC = %s\n", nextPC);
|
|
// Squash unless we're already squashing
|
|
squashFromDecode(fromDecode->decodeInfo[tid].nextPC,
|
|
fromDecode->decodeInfo[tid].doneSeqNum,
|
|
tid);
|
|
|
|
return true;
|
|
}
|
|
}
|
|
|
|
if (checkStall(tid) &&
|
|
fetchStatus[tid] != IcacheWaitResponse &&
|
|
fetchStatus[tid] != IcacheWaitRetry) {
|
|
DPRINTF(Fetch, "[tid:%i]: Setting to blocked\n",tid);
|
|
|
|
fetchStatus[tid] = Blocked;
|
|
|
|
return true;
|
|
}
|
|
|
|
if (fetchStatus[tid] == Blocked ||
|
|
fetchStatus[tid] == Squashing) {
|
|
// Switch status to running if fetch isn't being told to block or
|
|
// squash this cycle.
|
|
DPRINTF(Fetch, "[tid:%i]: Done squashing, switching to running.\n",
|
|
tid);
|
|
|
|
fetchStatus[tid] = Running;
|
|
|
|
return true;
|
|
}
|
|
|
|
// If we've reached this point, we have not gotten any signals that
|
|
// cause fetch to change its status. Fetch remains the same as before.
|
|
return false;
|
|
}
|
|
|
|
template<class Impl>
|
|
typename Impl::DynInstPtr
|
|
DefaultFetch<Impl>::buildInst(ThreadID tid, StaticInstPtr staticInst,
|
|
StaticInstPtr curMacroop, TheISA::PCState thisPC,
|
|
TheISA::PCState nextPC, bool trace)
|
|
{
|
|
// Get a sequence number.
|
|
InstSeqNum seq = cpu->getAndIncrementInstSeq();
|
|
|
|
// Create a new DynInst from the instruction fetched.
|
|
DynInstPtr instruction =
|
|
new DynInst(staticInst, thisPC, nextPC, seq, cpu);
|
|
instruction->setTid(tid);
|
|
|
|
instruction->setASID(tid);
|
|
|
|
instruction->setThreadState(cpu->thread[tid]);
|
|
|
|
DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created "
|
|
"[sn:%lli].\n", tid, thisPC.instAddr(),
|
|
thisPC.microPC(), seq);
|
|
|
|
DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid,
|
|
instruction->staticInst->
|
|
disassemble(thisPC.instAddr()));
|
|
|
|
#if TRACING_ON
|
|
if (trace) {
|
|
instruction->traceData =
|
|
cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid),
|
|
instruction->staticInst, thisPC, curMacroop);
|
|
}
|
|
#else
|
|
instruction->traceData = NULL;
|
|
#endif
|
|
|
|
// Add instruction to the CPU's list of instructions.
|
|
instruction->setInstListIt(cpu->addInst(instruction));
|
|
|
|
// Write the instruction to the first slot in the queue
|
|
// that heads to decode.
|
|
assert(numInst < fetchWidth);
|
|
toDecode->insts[toDecode->size++] = instruction;
|
|
|
|
return instruction;
|
|
}
|
|
|
|
template<class Impl>
|
|
void
|
|
DefaultFetch<Impl>::fetch(bool &status_change)
|
|
{
|
|
//////////////////////////////////////////
|
|
// Start actual fetch
|
|
//////////////////////////////////////////
|
|
ThreadID tid = getFetchingThread(fetchPolicy);
|
|
|
|
if (tid == InvalidThreadID || drainPending) {
|
|
DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
|
|
|
|
// Breaks looping condition in tick()
|
|
threadFetched = numFetchingThreads;
|
|
return;
|
|
}
|
|
|
|
DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
|
|
|
|
// The current PC.
|
|
TheISA::PCState thisPC = pc[tid];
|
|
|
|
Addr pcOffset = fetchOffset[tid];
|
|
Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
|
|
|
|
bool inRom = isRomMicroPC(thisPC.microPC());
|
|
|
|
// If returning from the delay of a cache miss, then update the status
|
|
// to running, otherwise do the cache access. Possibly move this up
|
|
// to tick() function.
|
|
if (fetchStatus[tid] == IcacheAccessComplete) {
|
|
DPRINTF(Fetch, "[tid:%i]: Icache miss is complete.\n", tid);
|
|
|
|
fetchStatus[tid] = Running;
|
|
status_change = true;
|
|
} else if (fetchStatus[tid] == Running) {
|
|
// Align the fetch PC so its at the start of a cache block.
|
|
Addr block_PC = icacheBlockAlignPC(fetchAddr);
|
|
|
|
// Unless buffer already got the block, fetch it from icache.
|
|
if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid]) && !inRom) {
|
|
DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
|
|
"instruction, starting at PC %s.\n", tid, thisPC);
|
|
|
|
fetchCacheLine(fetchAddr, tid, thisPC.instAddr());
|
|
|
|
if (fetchStatus[tid] == IcacheWaitResponse)
|
|
++icacheStallCycles;
|
|
else if (fetchStatus[tid] == ItlbWait)
|
|
++fetchTlbCycles;
|
|
else
|
|
++fetchMiscStallCycles;
|
|
return;
|
|
} else if (checkInterrupt(thisPC.instAddr()) || isSwitchedOut()) {
|
|
++fetchMiscStallCycles;
|
|
return;
|
|
}
|
|
} else {
|
|
if (fetchStatus[tid] == Idle) {
|
|
++fetchIdleCycles;
|
|
DPRINTF(Fetch, "[tid:%i]: Fetch is idle!\n", tid);
|
|
} else if (fetchStatus[tid] == Blocked) {
|
|
++fetchBlockedCycles;
|
|
DPRINTF(Fetch, "[tid:%i]: Fetch is blocked!\n", tid);
|
|
} else if (fetchStatus[tid] == Squashing) {
|
|
++fetchSquashCycles;
|
|
DPRINTF(Fetch, "[tid:%i]: Fetch is squashing!\n", tid);
|
|
} else if (fetchStatus[tid] == IcacheWaitResponse) {
|
|
++icacheStallCycles;
|
|
DPRINTF(Fetch, "[tid:%i]: Fetch is waiting cache response!\n",
|
|
tid);
|
|
} else if (fetchStatus[tid] == ItlbWait) {
|
|
DPRINTF(Fetch, "[tid:%i]: Fetch is waiting ITLB walk to "
|
|
"finish! \n", tid);
|
|
++fetchTlbCycles;
|
|
} else if (fetchStatus[tid] == TrapPending) {
|
|
DPRINTF(Fetch, "[tid:%i]: Fetch is waiting for a pending trap\n",
|
|
tid);
|
|
}
|
|
|
|
|
|
// Status is Idle, Squashing, Blocked, ItlbWait or IcacheWaitResponse
|
|
// so fetch should do nothing.
|
|
return;
|
|
}
|
|
|
|
++fetchCycles;
|
|
|
|
TheISA::PCState nextPC = thisPC;
|
|
|
|
StaticInstPtr staticInst = NULL;
|
|
StaticInstPtr curMacroop = macroop[tid];
|
|
|
|
// If the read of the first instruction was successful, then grab the
|
|
// instructions from the rest of the cache line and put them into the
|
|
// queue heading to decode.
|
|
|
|
DPRINTF(Fetch, "[tid:%i]: Adding instructions to queue to "
|
|
"decode.\n", tid);
|
|
|
|
// Need to keep track of whether or not a predicted branch
|
|
// ended this fetch block.
|
|
bool predictedBranch = false;
|
|
|
|
TheISA::MachInst *cacheInsts =
|
|
reinterpret_cast<TheISA::MachInst *>(cacheData[tid]);
|
|
|
|
const unsigned numInsts = cacheBlkSize / instSize;
|
|
unsigned blkOffset = (fetchAddr - cacheDataPC[tid]) / instSize;
|
|
|
|
// Loop through instruction memory from the cache.
|
|
while (blkOffset < numInsts &&
|
|
numInst < fetchWidth &&
|
|
!predictedBranch) {
|
|
|
|
// If we need to process more memory, do it now.
|
|
if (!(curMacroop || inRom) && !predecoder.extMachInstReady()) {
|
|
if (ISA_HAS_DELAY_SLOT && pcOffset == 0) {
|
|
// Walk past any annulled delay slot instructions.
|
|
Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask;
|
|
while (fetchAddr != pcAddr && blkOffset < numInsts) {
|
|
blkOffset++;
|
|
fetchAddr += instSize;
|
|
}
|
|
if (blkOffset >= numInsts)
|
|
break;
|
|
}
|
|
MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
|
|
|
|
predecoder.setTC(cpu->thread[tid]->getTC());
|
|
predecoder.moreBytes(thisPC, fetchAddr, inst);
|
|
|
|
if (predecoder.needMoreBytes()) {
|
|
blkOffset++;
|
|
fetchAddr += instSize;
|
|
pcOffset += instSize;
|
|
}
|
|
}
|
|
|
|
// Extract as many instructions and/or microops as we can from
|
|
// the memory we've processed so far.
|
|
do {
|
|
if (!(curMacroop || inRom)) {
|
|
if (predecoder.extMachInstReady()) {
|
|
ExtMachInst extMachInst;
|
|
|
|
extMachInst = predecoder.getExtMachInst(thisPC);
|
|
staticInst = StaticInstPtr(extMachInst,
|
|
thisPC.instAddr());
|
|
|
|
// Increment stat of fetched instructions.
|
|
++fetchedInsts;
|
|
|
|
if (staticInst->isMacroop()) {
|
|
curMacroop = staticInst;
|
|
} else {
|
|
pcOffset = 0;
|
|
}
|
|
} else {
|
|
// We need more bytes for this instruction.
|
|
break;
|
|
}
|
|
}
|
|
if (curMacroop || inRom) {
|
|
if (inRom) {
|
|
staticInst = cpu->microcodeRom.fetchMicroop(
|
|
thisPC.microPC(), curMacroop);
|
|
} else {
|
|
staticInst = curMacroop->fetchMicroop(thisPC.microPC());
|
|
}
|
|
if (staticInst->isLastMicroop()) {
|
|
curMacroop = NULL;
|
|
pcOffset = 0;
|
|
}
|
|
}
|
|
|
|
DynInstPtr instruction =
|
|
buildInst(tid, staticInst, curMacroop,
|
|
thisPC, nextPC, true);
|
|
|
|
numInst++;
|
|
|
|
nextPC = thisPC;
|
|
|
|
// If we're branching after this instruction, quite fetching
|
|
// from the same block then.
|
|
predictedBranch |= thisPC.branching();
|
|
predictedBranch |=
|
|
lookupAndUpdateNextPC(instruction, nextPC);
|
|
if (predictedBranch) {
|
|
DPRINTF(Fetch, "Branch detected with PC = %s\n", thisPC);
|
|
}
|
|
|
|
// Move to the next instruction, unless we have a branch.
|
|
thisPC = nextPC;
|
|
|
|
if (instruction->isQuiesce()) {
|
|
DPRINTF(Fetch,
|
|
"Quiesce instruction encountered, halting fetch!");
|
|
fetchStatus[tid] = QuiescePending;
|
|
status_change = true;
|
|
break;
|
|
}
|
|
} while ((curMacroop || predecoder.extMachInstReady()) &&
|
|
numInst < fetchWidth);
|
|
}
|
|
|
|
if (predictedBranch) {
|
|
DPRINTF(Fetch, "[tid:%i]: Done fetching, predicted branch "
|
|
"instruction encountered.\n", tid);
|
|
} else if (numInst >= fetchWidth) {
|
|
DPRINTF(Fetch, "[tid:%i]: Done fetching, reached fetch bandwidth "
|
|
"for this cycle.\n", tid);
|
|
} else if (blkOffset >= cacheBlkSize) {
|
|
DPRINTF(Fetch, "[tid:%i]: Done fetching, reached the end of cache "
|
|
"block.\n", tid);
|
|
}
|
|
|
|
macroop[tid] = curMacroop;
|
|
fetchOffset[tid] = pcOffset;
|
|
|
|
if (numInst > 0) {
|
|
wroteToTimeBuffer = true;
|
|
}
|
|
|
|
pc[tid] = thisPC;
|
|
}
|
|
|
|
template<class Impl>
|
|
void
|
|
DefaultFetch<Impl>::recvRetry()
|
|
{
|
|
if (retryPkt != NULL) {
|
|
assert(cacheBlocked);
|
|
assert(retryTid != InvalidThreadID);
|
|
assert(fetchStatus[retryTid] == IcacheWaitRetry);
|
|
|
|
if (icachePort->sendTiming(retryPkt)) {
|
|
fetchStatus[retryTid] = IcacheWaitResponse;
|
|
retryPkt = NULL;
|
|
retryTid = InvalidThreadID;
|
|
cacheBlocked = false;
|
|
}
|
|
} else {
|
|
assert(retryTid == InvalidThreadID);
|
|
// Access has been squashed since it was sent out. Just clear
|
|
// the cache being blocked.
|
|
cacheBlocked = false;
|
|
}
|
|
}
|
|
|
|
///////////////////////////////////////
|
|
// //
|
|
// SMT FETCH POLICY MAINTAINED HERE //
|
|
// //
|
|
///////////////////////////////////////
|
|
template<class Impl>
|
|
ThreadID
|
|
DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
|
|
{
|
|
if (numThreads > 1) {
|
|
switch (fetch_priority) {
|
|
|
|
case SingleThread:
|
|
return 0;
|
|
|
|
case RoundRobin:
|
|
return roundRobin();
|
|
|
|
case IQ:
|
|
return iqCount();
|
|
|
|
case LSQ:
|
|
return lsqCount();
|
|
|
|
case Branch:
|
|
return branchCount();
|
|
|
|
default:
|
|
return InvalidThreadID;
|
|
}
|
|
} else {
|
|
list<ThreadID>::iterator thread = activeThreads->begin();
|
|
if (thread == activeThreads->end()) {
|
|
return InvalidThreadID;
|
|
}
|
|
|
|
ThreadID tid = *thread;
|
|
|
|
if (fetchStatus[tid] == Running ||
|
|
fetchStatus[tid] == IcacheAccessComplete ||
|
|
fetchStatus[tid] == Idle) {
|
|
return tid;
|
|
} else {
|
|
return InvalidThreadID;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
template<class Impl>
|
|
ThreadID
|
|
DefaultFetch<Impl>::roundRobin()
|
|
{
|
|
list<ThreadID>::iterator pri_iter = priorityList.begin();
|
|
list<ThreadID>::iterator end = priorityList.end();
|
|
|
|
ThreadID high_pri;
|
|
|
|
while (pri_iter != end) {
|
|
high_pri = *pri_iter;
|
|
|
|
assert(high_pri <= numThreads);
|
|
|
|
if (fetchStatus[high_pri] == Running ||
|
|
fetchStatus[high_pri] == IcacheAccessComplete ||
|
|
fetchStatus[high_pri] == Idle) {
|
|
|
|
priorityList.erase(pri_iter);
|
|
priorityList.push_back(high_pri);
|
|
|
|
return high_pri;
|
|
}
|
|
|
|
pri_iter++;
|
|
}
|
|
|
|
return InvalidThreadID;
|
|
}
|
|
|
|
template<class Impl>
|
|
ThreadID
|
|
DefaultFetch<Impl>::iqCount()
|
|
{
|
|
std::priority_queue<unsigned> PQ;
|
|
std::map<unsigned, ThreadID> threadMap;
|
|
|
|
list<ThreadID>::iterator threads = activeThreads->begin();
|
|
list<ThreadID>::iterator end = activeThreads->end();
|
|
|
|
while (threads != end) {
|
|
ThreadID tid = *threads++;
|
|
unsigned iqCount = fromIEW->iewInfo[tid].iqCount;
|
|
|
|
PQ.push(iqCount);
|
|
threadMap[iqCount] = tid;
|
|
}
|
|
|
|
while (!PQ.empty()) {
|
|
ThreadID high_pri = threadMap[PQ.top()];
|
|
|
|
if (fetchStatus[high_pri] == Running ||
|
|
fetchStatus[high_pri] == IcacheAccessComplete ||
|
|
fetchStatus[high_pri] == Idle)
|
|
return high_pri;
|
|
else
|
|
PQ.pop();
|
|
|
|
}
|
|
|
|
return InvalidThreadID;
|
|
}
|
|
|
|
template<class Impl>
|
|
ThreadID
|
|
DefaultFetch<Impl>::lsqCount()
|
|
{
|
|
std::priority_queue<unsigned> PQ;
|
|
std::map<unsigned, ThreadID> threadMap;
|
|
|
|
list<ThreadID>::iterator threads = activeThreads->begin();
|
|
list<ThreadID>::iterator end = activeThreads->end();
|
|
|
|
while (threads != end) {
|
|
ThreadID tid = *threads++;
|
|
unsigned ldstqCount = fromIEW->iewInfo[tid].ldstqCount;
|
|
|
|
PQ.push(ldstqCount);
|
|
threadMap[ldstqCount] = tid;
|
|
}
|
|
|
|
while (!PQ.empty()) {
|
|
ThreadID high_pri = threadMap[PQ.top()];
|
|
|
|
if (fetchStatus[high_pri] == Running ||
|
|
fetchStatus[high_pri] == IcacheAccessComplete ||
|
|
fetchStatus[high_pri] == Idle)
|
|
return high_pri;
|
|
else
|
|
PQ.pop();
|
|
}
|
|
|
|
return InvalidThreadID;
|
|
}
|
|
|
|
template<class Impl>
|
|
ThreadID
|
|
DefaultFetch<Impl>::branchCount()
|
|
{
|
|
#if 0
|
|
list<ThreadID>::iterator thread = activeThreads->begin();
|
|
assert(thread != activeThreads->end());
|
|
ThreadID tid = *thread;
|
|
#endif
|
|
|
|
panic("Branch Count Fetch policy unimplemented\n");
|
|
return InvalidThreadID;
|
|
}
|