ecbb8debf6
getting touched.
configs/common/FSConfig.py:
Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
Fix AsiIsNucleus spelling with respect to header file
Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
Flesh out priviledgedString with hypervisor checks
Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
add an IPR traceflag
src/mem/request.hh:
Fix a bad assert() in request
--HG--
extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28
126 lines
5 KiB
Python
126 lines
5 KiB
Python
# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Kevin Lim
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import m5
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from m5 import makeList
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from m5.objects import *
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from Benchmarks import *
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class CowIdeDisk(IdeDisk):
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image = CowDiskImage(child=RawDiskImage(read_only=True),
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read_only=False)
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def childImage(self, ci):
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self.image.child.image_file = ci
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class BaseTsunami(Tsunami):
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ethernet = NSGigE(configdata=NSGigEPciData(),
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pci_bus=0, pci_dev=1, pci_func=0)
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etherint = NSGigEInt(device=Parent.ethernet)
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ide = IdeController(disks=[Parent.disk0, Parent.disk2],
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pci_func=0, pci_dev=0, pci_bus=0)
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def makeLinuxAlphaSystem(mem_mode, mdesc = None):
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self = LinuxAlphaSystem()
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.iobus = Bus(bus_id=0)
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self.membus = Bus(bus_id=1)
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self.bridge = Bridge()
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self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
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self.bridge.side_a = self.iobus.port
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self.bridge.side_b = self.membus.port
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self.physmem.port = self.membus.port
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self.disk0 = CowIdeDisk(driveID='master')
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self.disk2 = CowIdeDisk(driveID='master')
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self.disk0.childImage(mdesc.disk())
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self.disk2.childImage(disk('linux-bigswap2.img'))
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self.tsunami = BaseTsunami()
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self.tsunami.attachIO(self.iobus)
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self.tsunami.ide.pio = self.iobus.port
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self.tsunami.ethernet.pio = self.iobus.port
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self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
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read_only = True))
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self.intrctrl = IntrControl()
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self.mem_mode = mem_mode
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self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
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self.kernel = binary('vmlinux')
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self.pal = binary('ts_osfpal')
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self.console = binary('console')
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self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
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return self
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def makeSparcSystem(mem_mode, mdesc = None):
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self = SparcSystem()
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.iobus = Bus(bus_id=0)
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self.membus = Bus(bus_id=1)
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self.bridge = Bridge()
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self.t1000 = T1000()
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self.t1000.attachIO(self.iobus)
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self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
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self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
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self.bridge.side_a = self.iobus.port
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self.bridge.side_b = self.membus.port
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self.physmem.port = self.membus.port
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self.physmem2.port = self.membus.port
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self.rom.port = self.membus.port
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self.nvram.port = self.membus.port
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self.hypervisor_desc.port = self.membus.port
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self.partition_desc.port = self.membus.port
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self.intrctrl = IntrControl()
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self.mem_mode = mem_mode
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self.reset_bin = binary('reset.bin')
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self.hypervisor_bin = binary('q.bin')
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self.openboot_bin = binary('openboot.bin')
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self.nvram_bin = binary('nvram1')
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self.hypervisor_desc_bin = binary('1up-hv.bin')
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self.partition_desc_bin = binary('1up-md.bin')
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return self
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def makeDualRoot(testSystem, driveSystem, dumpfile):
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self = Root()
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self.testsys = testSystem
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self.drivesys = driveSystem
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self.etherlink = EtherLink(int1 = Parent.testsys.tsunami.etherint[0],
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int2 = Parent.drivesys.tsunami.etherint[0])
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if dumpfile:
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self.etherdump = EtherDump(file=dumpfile)
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self.etherlink.dump = Parent.etherdump
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self.clock = '1THz'
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return self
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