gem5/src
Ron Dreslinski 4201ec84b2 Fix some unset values in the request in the timing CPU.
Properly implement the MSHR allocate function.

src/cpu/simple/timing.cc:
    Set the thread context in the CPU.

    Need to do this properly, currently I just set it to Cpu=0 Thread=0.  This will just cause all the stats in the cache based on these to just yield totals and not a distribution.
src/mem/cache/miss/mshr.cc:
    Properly implement the allocate function for the MSHR.

--HG--
extra : convert_revision : bcece518e54ed1404db3196f996a77b4dd5c1c1e
2006-07-05 15:13:27 -04:00
..
arch Make full CPU handle SE faults 2006-06-27 14:59:38 -04:00
base Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads) 2006-07-02 23:11:24 -04:00
cpu Fix some unset values in the request in the timing CPU. 2006-07-05 15:13:27 -04:00
dev minor device fixups 2006-06-18 11:10:08 -04:00
kern Merge zizzer.eecs.umich.edu:/bk/newmem 2006-06-17 18:28:21 -04:00
mem Fix some unset values in the request in the timing CPU. 2006-07-05 15:13:27 -04:00
python Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads) 2006-07-02 23:11:24 -04:00
sim Fix for FS O3CPU compile ... missing forward class declaration/header file after files got split for ISA-independence 2006-07-03 12:19:35 -04:00
unittest Merge iceaxe.:/Volumes/work/research/m5/head 2006-06-11 22:01:34 -04:00
Doxyfile New directory structure: 2006-05-22 14:29:33 -04:00
SConscript Merge zizzer:/z/m5/Bitkeeper/newmem 2006-06-30 10:25:50 -04:00