54227f9e57
This patch updates the stats to reflect the changes in the clock speed and width for the bus connecting the L1 and L2 caches.
408 lines
46 KiB
Text
408 lines
46 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000026 # Number of seconds simulated
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sim_ticks 25969000 # Number of ticks simulated
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final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 147661 # Simulator instruction rate (inst/s)
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host_op_rate 183366 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 839095918 # Simulator tick rate (ticks/s)
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host_mem_usage 231680 # Number of bytes of host memory used
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host_seconds 0.03 # Real time elapsed on the host
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sim_insts 4565 # Number of instructions simulated
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sim_ops 5672 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
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system.physmem.bytes_read::total 22400 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 350 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 554507297 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 308059610 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 862566907 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 554507297 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 554507297 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 554507297 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 308059610 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 862566907 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 13 # Number of system calls
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system.cpu.numCycles 51938 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 4565 # Number of instructions committed
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system.cpu.committedOps 5672 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
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system.cpu.num_func_calls 203 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls
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system.cpu.num_int_insts 4976 # number of integer instructions
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system.cpu.num_fp_insts 16 # number of float instructions
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system.cpu.num_int_register_reads 28656 # number of times the integer registers were read
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system.cpu.num_int_register_writes 5334 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.num_mem_refs 2138 # number of memory refs
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system.cpu.num_load_insts 1200 # Number of load instructions
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system.cpu.num_store_insts 938 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 51938 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 1 # number of replacements
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system.cpu.icache.tagsinuse 114.614391 # Cycle average of tags in use
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system.cpu.icache.total_refs 4364 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 18.107884 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.055964 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 4364 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 4364 # number of overall hits
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system.cpu.icache.overall_hits::total 4364 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses
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system.cpu.icache.overall_misses::total 241 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 12583000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 12583000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 12583000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 12583000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 12583000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 12583000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 4605 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 4605 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 4605 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052334 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.052334 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52211.618257 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_miss_latency::total 52211.618257 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total 52211.618257 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total 52211.618257 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12101000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 12101000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12101000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 12101000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12101000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.tagsinuse 83.000387 # Cycle average of tags in use
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system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.020264 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits
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system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
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system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
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system.cpu.dcache.demand_hits::cpu.data 1918 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 1918 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 1918 # number of overall hits
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system.cpu.dcache.overall_hits::total 1918 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses
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system.cpu.dcache.overall_misses::total 141 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::cpu.data 2059 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 2059 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::cpu.data 2059 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 2059 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085515 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.085515 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085515 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085515 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 154.071129 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.004702 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 32 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 82 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 307 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 350 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11700000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 15964000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 11700000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 18200000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 11700000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 18200000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.905605 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|