4eff4fa12e
Doesn't support x86 due to static instruction representation. --HG-- rename : src/cpu/CPUTracers.py => src/cpu/InstPBTrace.py
107 lines
3.7 KiB
Protocol Buffer
107 lines
3.7 KiB
Protocol Buffer
// Copyright (c) 2014 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Ali Saidi
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// Put all the generated messages in a namespace
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package ProtoMessage;
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// Packet header with the identifier describing what object captured
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// the trace, the version of this file format, and the tick frequency
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// for all the packet time stamps.
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message InstHeader {
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required string obj_id = 1;
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required uint32 ver = 2 [default = 0];
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required uint64 tick_freq = 3;
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required bool has_mem = 4;
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}
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message Inst {
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required uint64 pc = 1;
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required fixed32 inst = 2;
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optional uint32 nodeid = 3;
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optional uint32 cpuid = 4;
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optional fixed64 tick = 5;
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enum InstType {
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None = 0;
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IntAlu = 1;
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IntMul = 2;
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IntDiv = 3;
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FloatAdd = 4;
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FloatCmp = 5;
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FloatCvt = 6;
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FloatMult = 7;
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FloatDiv = 8;
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FloatSqrt = 9;
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SIMDIntAdd = 10;
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SIMDIntAddAcc = 11;
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SIMDIntAlu = 12;
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SIMDIntCmp = 13;
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SIMDIntCvt = 14;
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SIMDMisc = 15;
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SIMDIntMult = 16;
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SIMDIntMultAcc = 17;
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SIMDIntShift = 18;
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SIMDIntShiftAcc = 19;
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SIMDSqrt = 20;
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SIMDFloatAdd = 21;
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SIMDFloatAlu = 22;
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SIMDFloatCmp = 23;
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SIMDFloatCvt = 24;
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SIMDFloatDiv = 25;
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SIMDFloatMisc = 26;
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SIMDFloatMult = 27;
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SIMDFloatMultAdd = 28;
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SIMDFloatSqrt = 29;
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MemRead = 30;
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MemWrite = 31;
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IprAccess = 32;
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InstPrefetch = 33;
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}
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optional InstType type = 6; // add, mul, fp add, load, store, simd add, …
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optional uint32 inst_flags = 7; // execution mode information
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// If the operation does one or more memory accesses
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message MemAccess {
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required uint64 addr = 1;
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required uint32 size = 2;
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optional uint32 mem_flags = 3;
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}
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repeated MemAccess mem_access = 8;
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}
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