df8df4fd0a
Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
1064 lines
121 KiB
Text
1064 lines
121 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.662030 # Number of seconds simulated
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sim_ticks 662030381000 # Number of ticks simulated
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final_tick 662030381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 173779 # Simulator instruction rate (inst/s)
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host_op_rate 173779 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 66269486 # Simulator tick rate (ticks/s)
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host_mem_usage 296312 # Number of bytes of host memory used
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host_seconds 9989.97 # Real time elapsed on the host
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sim_insts 1736043781 # Number of instructions simulated
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sim_ops 1736043781 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 125964224 # Number of bytes read from this memory
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system.physmem.bytes_read::total 126026048 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 65301568 # Number of bytes written to this memory
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system.physmem.bytes_written::total 65301568 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1968191 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 1969157 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1020337 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1020337 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 93385 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 190269552 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 190362937 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 93385 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 93385 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 98638325 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 98638325 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 98638325 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 93385 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 190269552 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 289001263 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 1969157 # Number of read requests accepted
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system.physmem.writeReqs 1020337 # Number of write requests accepted
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system.physmem.readBursts 1969157 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 1020337 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 125945216 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 80832 # Total number of bytes read from write queue
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system.physmem.bytesWritten 65299584 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 126026048 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 65301568 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 1263 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 119107 # Per bank write bursts
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system.physmem.perBankRdBursts::1 114513 # Per bank write bursts
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system.physmem.perBankRdBursts::2 116588 # Per bank write bursts
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system.physmem.perBankRdBursts::3 118130 # Per bank write bursts
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system.physmem.perBankRdBursts::4 118281 # Per bank write bursts
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system.physmem.perBankRdBursts::5 117894 # Per bank write bursts
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system.physmem.perBankRdBursts::6 120372 # Per bank write bursts
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system.physmem.perBankRdBursts::7 125027 # Per bank write bursts
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system.physmem.perBankRdBursts::8 127642 # Per bank write bursts
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system.physmem.perBankRdBursts::9 130604 # Per bank write bursts
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system.physmem.perBankRdBursts::10 129295 # Per bank write bursts
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system.physmem.perBankRdBursts::11 130929 # Per bank write bursts
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system.physmem.perBankRdBursts::12 126770 # Per bank write bursts
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system.physmem.perBankRdBursts::13 125862 # Per bank write bursts
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system.physmem.perBankRdBursts::14 123081 # Per bank write bursts
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system.physmem.perBankRdBursts::15 123799 # Per bank write bursts
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system.physmem.perBankWrBursts::0 61289 # Per bank write bursts
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system.physmem.perBankWrBursts::1 61597 # Per bank write bursts
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system.physmem.perBankWrBursts::2 60658 # Per bank write bursts
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system.physmem.perBankWrBursts::3 61339 # Per bank write bursts
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system.physmem.perBankWrBursts::4 61821 # Per bank write bursts
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system.physmem.perBankWrBursts::5 63209 # Per bank write bursts
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system.physmem.perBankWrBursts::6 64289 # Per bank write bursts
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system.physmem.perBankWrBursts::7 65739 # Per bank write bursts
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system.physmem.perBankWrBursts::8 65503 # Per bank write bursts
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system.physmem.perBankWrBursts::9 65920 # Per bank write bursts
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system.physmem.perBankWrBursts::10 65439 # Per bank write bursts
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system.physmem.perBankWrBursts::11 65771 # Per bank write bursts
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system.physmem.perBankWrBursts::12 64363 # Per bank write bursts
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system.physmem.perBankWrBursts::13 64352 # Per bank write bursts
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system.physmem.perBankWrBursts::14 64685 # Per bank write bursts
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system.physmem.perBankWrBursts::15 64332 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 662030291500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 1969157 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 1020337 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 1619145 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 248303 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 76115 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 24314 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 25811 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 27497 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 49263 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 56182 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 59042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 60255 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 60670 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 60945 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 61157 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 61369 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 61481 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 61969 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 63086 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 64803 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 62190 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 62948 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 61430 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 60023 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 153 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 38 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1776224 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 107.667141 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 82.863857 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 136.742577 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 1381396 77.77% 77.77% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 271071 15.26% 93.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 53950 3.04% 96.07% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 21226 1.20% 97.26% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 12955 0.73% 97.99% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 6597 0.37% 98.37% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 5003 0.28% 98.65% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 3759 0.21% 98.86% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 20267 1.14% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1776224 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 59925 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 32.795728 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 163.660245 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 59887 99.94% 99.94% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.97% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::3072-4095 9 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 59925 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 59925 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 17.026383 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.985304 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 1.212732 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 31950 53.32% 53.32% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::17 1595 2.66% 55.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 20819 34.74% 90.72% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 4577 7.64% 98.36% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20 750 1.25% 99.61% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::21 154 0.26% 99.87% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::22 27 0.05% 99.91% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::23 19 0.03% 99.94% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::24 7 0.01% 99.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::26 2 0.00% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::27 3 0.01% 99.96% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::30 4 0.01% 99.97% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::31 3 0.01% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::32 3 0.01% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::33 2 0.00% 99.99% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::34 1 0.00% 99.99% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::35 1 0.00% 99.99% # Writes before turning the bus around for reads
|
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system.physmem.wrPerTurnAround::36 4 0.01% 100.00% # Writes before turning the bus around for reads
|
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system.physmem.wrPerTurnAround::37 1 0.00% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 59925 # Writes before turning the bus around for reads
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system.physmem.totQLat 40790268000 # Total ticks spent queuing
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system.physmem.totMemAccLat 77688280500 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 9839470000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 20727.88 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 39477.88 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 190.24 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 98.64 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 190.36 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 98.64 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 2.26 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 1.49 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.77 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 24.76 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 795786 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 416180 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 40.44 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 40.79 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 221452.29 # Average gap between requests
|
|
system.physmem.pageHitRate 40.56 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 6511261680 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 3552771750 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 7409259000 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 3239617680 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 43240314000 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 299928124440 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 134120853750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 498002202300 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 752.239455 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 221171423750 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 22106500000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 418748256250 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 6916946400 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 3774127500 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 7939518600 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 3371965200 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 43240314000 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 306633623535 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 128238837000 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 500115332235 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 755.431368 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 211341940750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 22106500000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 428577885750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 410531758 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 318847451 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 16269165 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 283137932 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 279377578 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 98.671900 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 26373623 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 19 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu.dtb.read_hits 646133385 # DTB read hits
|
|
system.cpu.dtb.read_misses 12154937 # DTB read misses
|
|
system.cpu.dtb.read_acv 1 # DTB read access violations
|
|
system.cpu.dtb.read_accesses 658288322 # DTB read accesses
|
|
system.cpu.dtb.write_hits 218173916 # DTB write hits
|
|
system.cpu.dtb.write_misses 7514058 # DTB write misses
|
|
system.cpu.dtb.write_acv 0 # DTB write access violations
|
|
system.cpu.dtb.write_accesses 225687974 # DTB write accesses
|
|
system.cpu.dtb.data_hits 864307301 # DTB hits
|
|
system.cpu.dtb.data_misses 19668995 # DTB misses
|
|
system.cpu.dtb.data_acv 1 # DTB access violations
|
|
system.cpu.dtb.data_accesses 883976296 # DTB accesses
|
|
system.cpu.itb.fetch_hits 422458110 # ITB hits
|
|
system.cpu.itb.fetch_misses 45 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 422458155 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 29 # Number of system calls
|
|
system.cpu.numCycles 1324060763 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 433748906 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 3419441963 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 410531758 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 305751201 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 867248304 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 45995858 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 88 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 1804 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 422458110 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 8422260 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 1323997070 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 2.582666 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.157790 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 696991073 52.64% 52.64% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 48002120 3.63% 56.27% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 24407254 1.84% 58.11% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 45263157 3.42% 61.53% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 142993214 10.80% 72.33% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 66222276 5.00% 77.33% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 43788088 3.31% 80.64% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 29616004 2.24% 82.88% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 226713884 17.12% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 1323997070 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.310055 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 2.582542 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 355597650 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 384696746 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 525812607 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 34892959 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 22997108 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 62293389 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 869 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 3264034948 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 2192 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 22997108 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 373957968 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 205165673 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 7731 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 538730067 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 183138523 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 3181033284 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 1755579 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 18983042 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 140285341 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 27927823 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 2377354751 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 4126620289 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 4126448707 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 171581 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 1001151788 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 192 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 191 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 99207749 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 719206023 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 272877739 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 90880933 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 59162115 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 2889782486 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 178 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 2624016708 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 1570062 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 1139342915 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 505618557 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 149 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 1323997070 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.981890 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 2.151111 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 519747645 39.26% 39.26% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 169377682 12.79% 52.05% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 158338012 11.96% 64.01% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 149173722 11.27% 75.27% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 126185648 9.53% 84.81% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 84437665 6.38% 91.18% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 68199937 5.15% 96.33% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 33982775 2.57% 98.90% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 14553984 1.10% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 1323997070 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 13171575 35.70% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.70% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 19111155 51.80% 87.50% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 4612971 12.50% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 1719329788 65.52% 65.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 125 0.00% 65.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 895316 0.03% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 18 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 672939161 25.65% 91.20% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 230852080 8.80% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 2624016708 # Type of FU issued
|
|
system.cpu.iq.rate 1.981795 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 36895701 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.014061 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 6608517036 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 4027973051 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 2521923586 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 1979213 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 1297888 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 892539 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 2659929620 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 982789 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 69543206 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 274610360 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 379362 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 147727 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 112149237 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 353 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 6023017 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 22997108 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 147758887 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 18474565 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 3040988458 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 6691344 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 719206023 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 272877739 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 178 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 822290 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 17921565 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 147727 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 10901488 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 8843129 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 19744617 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 2578330269 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 658288327 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 45686439 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 151205794 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 883976375 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 315983093 # Number of branches executed
|
|
system.cpu.iew.exec_stores 225688048 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.947290 # Inst execution rate
|
|
system.cpu.iew.wb_sent 2552817971 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 2522816125 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1489246506 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 1920479792 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.905363 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.775455 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 1005136223 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 16268344 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 1185116972 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.535528 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.558449 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 695949152 58.72% 58.72% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 159874809 13.49% 72.21% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 79784402 6.73% 78.95% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 52116706 4.40% 83.34% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 28440614 2.40% 85.74% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 19407125 1.64% 87.38% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 20027045 1.69% 89.07% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 23110908 1.95% 91.02% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 106406211 8.98% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 1185116972 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
|
|
system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 605324165 # Number of memory references committed
|
|
system.cpu.commit.loads 444595663 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 214632552 # Number of branches committed
|
|
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 1129914149 62.09% 66.69% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 75 0.00% 66.69% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.69% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 805244 0.04% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 444595663 24.43% 91.17% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 106406211 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 3817847910 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 5788846951 # The number of ROB writes
|
|
system.cpu.timesIdled 724 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 63693 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.762689 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.762689 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.311151 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.311151 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 3467581476 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 2022302956 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 46080 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 592 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 9209012 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4087.412521 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 713854428 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 9213108 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 77.482477 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 5099544250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4087.412521 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.997903 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.997903 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 751 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2935 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 1472845170 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 1472845170 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 558341279 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 558341279 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 155513145 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 155513145 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 713854424 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 713854424 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 713854424 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 713854424 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 12746245 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 12746245 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 5215357 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 5215357 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 17961602 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 17961602 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 17961602 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 17961602 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 384451562750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 384451562750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 289305166008 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 289305166008 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 69500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 69500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 673756728758 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 673756728758 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 673756728758 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 673756728758 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 571087524 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 571087524 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 731816026 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 731816026 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 731816026 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 731816026 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022319 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.022319 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032448 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.032448 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.024544 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.024544 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.024544 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.024544 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30161.946734 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 30161.946734 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55471.785730 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 55471.785730 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 37510.948564 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 37510.948564 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 37510.948564 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 37510.948564 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 14120110 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 8634302 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 1055091 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 67341 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.382836 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 128.217609 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 3742780 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 3742780 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5412238 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 5412238 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3336257 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 3336257 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 8748495 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 8748495 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 8748495 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 8748495 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334007 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 7334007 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879100 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1879100 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 9213107 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 9213107 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 9213107 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 9213107 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168659488250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 168659488250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77208966781 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 77208966781 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 67500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 67500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245868455031 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 245868455031 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245868455031 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 245868455031 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22996.908545 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22996.908545 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41088.269268 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41088.269268 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 67500 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 67500 # average LoadLockedReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26686.812064 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26686.812064 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26686.812064 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26686.812064 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 1 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 770.158211 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 422456585 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 966 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 437325.657350 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 770.158211 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.376054 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.376054 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 899 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 844917184 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 844917184 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 422456585 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 422456585 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 422456585 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 422456585 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 422456585 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 422456585 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1524 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1524 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1524 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1524 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1524 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1524 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 107000999 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 107000999 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 107000999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 107000999 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 107000999 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 107000999 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 422458109 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 422458109 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 422458109 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 422458109 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 422458109 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 422458109 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70210.629265 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 70210.629265 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70210.629265 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 70210.629265 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70210.629265 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 70210.629265 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 469 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 558 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 558 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 558 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 558 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 558 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 558 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 966 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 966 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72141249 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 72141249 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72141249 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 72141249 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72141249 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 72141249 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74680.381988 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74680.381988 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74680.381988 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 74680.381988 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74680.381988 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 74680.381988 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 1936441 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 31406.538176 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 9110982 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 1966231 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 4.633729 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 27876136750 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 14557.398525 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.847630 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 16822.292021 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.444257 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000819 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.513376 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.958451 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29790 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 970 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 611 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17653 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10389 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909119 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 107500175 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 107500175 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 6137091 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 6137091 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 3742780 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 3742780 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 1107826 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 1107826 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 7244917 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 7244917 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 7244917 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 7244917 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 966 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1196905 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1197871 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 771286 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 771286 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 966 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1968191 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 1969157 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 966 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1968191 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 1969157 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71167250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98889965000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 98961132250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 63707909498 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 63707909498 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 71167250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 162597874498 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 162669041748 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 71167250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 162597874498 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 162669041748 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 966 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 7333996 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 7334962 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 3742780 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 3742780 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1879112 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1879112 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 966 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 9213108 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 9214074 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 966 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 9213108 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 9214074 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163200 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.163310 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.410452 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.410452 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.213629 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.213712 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.213629 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.213712 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73672.101449 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82621.398524 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 82614.181535 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82599.592755 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82599.592755 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73672.101449 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82612.853376 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 82608.467353 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73672.101449 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82612.853376 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 82608.467353 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1020337 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1020337 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1196905 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1197871 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 771286 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 771286 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1968191 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 1969157 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1968191 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 1969157 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58998750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 83895775000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83954773750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54083955498 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54083955498 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58998750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137979730498 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 138038729248 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58998750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137979730498 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 138038729248 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163200 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163310 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410452 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410452 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213629 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.213712 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213629 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.213712 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61075.310559 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70093.929761 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70086.656869 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70121.790747 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70121.790747 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61075.310559 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70104.847801 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70100.418224 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61075.310559 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70104.847801 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70100.418224 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 7334962 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 7334962 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 3742780 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 1879112 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 1879112 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1932 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22168996 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 22170928 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829176832 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 829238656 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 12957003 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 12957003 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 12957003 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 10221354853 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1610750 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 14117356000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadReq 1197871 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 1197871 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 1020337 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 771286 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 771286 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4958651 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 4958651 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191327616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 191327616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 2989494 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 2989494 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 2989494 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 11823428000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 18423304250 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 2.8 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|