df8df4fd0a
Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
1211 lines
139 KiB
Plaintext
1211 lines
139 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.232212 # Number of seconds simulated
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sim_ticks 232211555000 # Number of ticks simulated
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final_tick 232211555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 135087 # Simulator instruction rate (inst/s)
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host_op_rate 146347 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 62087234 # Simulator tick rate (ticks/s)
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host_mem_usage 317808 # Number of bytes of host memory used
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host_seconds 3740.09 # Real time elapsed on the host
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sim_insts 505237723 # Number of instructions simulated
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sim_ops 547350944 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 681088 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 9254400 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.l2cache.prefetcher 16474624 # Number of bytes read from this memory
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system.physmem.bytes_read::total 26410112 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 681088 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 681088 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 18728832 # Number of bytes written to this memory
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system.physmem.bytes_written::total 18728832 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 10642 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 144600 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.l2cache.prefetcher 257416 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 412658 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 292638 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 292638 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 2933050 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 39853314 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.l2cache.prefetcher 70946616 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 113732979 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 2933050 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 2933050 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 80654178 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 80654178 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 80654178 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 2933050 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 39853314 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.l2cache.prefetcher 70946616 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 194387157 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 412658 # Number of read requests accepted
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system.physmem.writeReqs 292638 # Number of write requests accepted
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system.physmem.readBursts 412658 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 292638 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 26271168 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 138944 # Total number of bytes read from write queue
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system.physmem.bytesWritten 18727424 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 26410112 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 18728832 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 2171 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 26576 # Per bank write bursts
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system.physmem.perBankRdBursts::1 25575 # Per bank write bursts
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system.physmem.perBankRdBursts::2 25174 # Per bank write bursts
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system.physmem.perBankRdBursts::3 24876 # Per bank write bursts
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system.physmem.perBankRdBursts::4 27202 # Per bank write bursts
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system.physmem.perBankRdBursts::5 26589 # Per bank write bursts
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system.physmem.perBankRdBursts::6 25428 # Per bank write bursts
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system.physmem.perBankRdBursts::7 24234 # Per bank write bursts
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system.physmem.perBankRdBursts::8 25846 # Per bank write bursts
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system.physmem.perBankRdBursts::9 24812 # Per bank write bursts
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system.physmem.perBankRdBursts::10 25055 # Per bank write bursts
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system.physmem.perBankRdBursts::11 26081 # Per bank write bursts
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system.physmem.perBankRdBursts::12 26502 # Per bank write bursts
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system.physmem.perBankRdBursts::13 25872 # Per bank write bursts
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system.physmem.perBankRdBursts::14 25198 # Per bank write bursts
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system.physmem.perBankRdBursts::15 25467 # Per bank write bursts
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system.physmem.perBankWrBursts::0 18795 # Per bank write bursts
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system.physmem.perBankWrBursts::1 18343 # Per bank write bursts
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system.physmem.perBankWrBursts::2 17877 # Per bank write bursts
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system.physmem.perBankWrBursts::3 18076 # Per bank write bursts
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system.physmem.perBankWrBursts::4 18802 # Per bank write bursts
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system.physmem.perBankWrBursts::5 18306 # Per bank write bursts
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system.physmem.perBankWrBursts::6 18071 # Per bank write bursts
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system.physmem.perBankWrBursts::7 17638 # Per bank write bursts
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system.physmem.perBankWrBursts::8 18138 # Per bank write bursts
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system.physmem.perBankWrBursts::9 17849 # Per bank write bursts
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system.physmem.perBankWrBursts::10 18079 # Per bank write bursts
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system.physmem.perBankWrBursts::11 18708 # Per bank write bursts
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system.physmem.perBankWrBursts::12 18879 # Per bank write bursts
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system.physmem.perBankWrBursts::13 18261 # Per bank write bursts
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system.physmem.perBankWrBursts::14 18465 # Per bank write bursts
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system.physmem.perBankWrBursts::15 18329 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 232211534500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 412658 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 292638 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 311514 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 49355 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 13370 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 9258 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 7406 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 6188 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 5306 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 4451 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 3459 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 6204 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 6468 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 13583 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 15531 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 16421 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 16883 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 17156 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 17339 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 17608 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 17806 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 18103 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 18634 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 19068 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 19781 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 18496 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 18131 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 17723 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 17546 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 85 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 307877 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 146.155822 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 102.817953 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 181.897933 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 185209 60.16% 60.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 81919 26.61% 86.76% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 16650 5.41% 92.17% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 7285 2.37% 94.54% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 4666 1.52% 96.05% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 2373 0.77% 96.83% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1833 0.60% 97.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1570 0.51% 97.93% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 6372 2.07% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 307877 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 17388 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 23.607430 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 116.348412 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-511 17387 99.99% 99.99% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 17388 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 17388 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.828617 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.789393 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 1.188635 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 10816 62.20% 62.20% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::17 278 1.60% 63.80% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 5484 31.54% 95.34% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 506 2.91% 98.25% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20 126 0.72% 98.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::21 66 0.38% 99.36% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::22 41 0.24% 99.59% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::23 33 0.19% 99.78% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::24 20 0.12% 99.90% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::25 12 0.07% 99.97% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::26 5 0.03% 99.99% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 17388 # Writes before turning the bus around for reads
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system.physmem.totQLat 9526506707 # Total ticks spent queuing
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system.physmem.totMemAccLat 17223137957 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 2052435000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 23207.82 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 41957.82 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 113.13 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 80.65 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 113.73 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 80.65 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 1.51 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing
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system.physmem.readRowHits 299737 # Number of row buffer hits during reads
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system.physmem.writeRowHits 95481 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 73.02 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 32.63 # Row buffer hit rate for writes
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system.physmem.avgGap 329239.83 # Average gap between requests
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system.physmem.pageHitRate 56.21 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 1161435240 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 633719625 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 1603960800 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 945386640 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 74505009510 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 73970535750 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 167986832445 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 723.427350 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 122529683190 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 7753980000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 101926029060 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 1165888080 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 636149250 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1597541400 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 950557680 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 73837287855 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 74556205500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 167910414645 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 723.098525 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 123510236330 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 7753980000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 100945998170 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 175052211 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 131310953 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 7443013 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 90523756 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 83852008 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 92.629837 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 12106573 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 104182 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 548 # Number of system calls
|
|
system.cpu.numCycles 464423111 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 7829450 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 731665108 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 175052211 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 95958581 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 448342475 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 14938309 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 5167 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 75 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 11385 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 236661621 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 34410 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 463657706 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.708988 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.176697 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 91809808 19.80% 19.80% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 132662466 28.61% 48.41% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 57833448 12.47% 60.89% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 181351984 39.11% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 463657706 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.376924 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.575428 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 32373161 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 115247897 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 287024980 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 22030943 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 6980725 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 24047273 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 496181 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 715717692 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 29980742 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 6980725 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 63423134 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 52089726 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 40328416 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 276637091 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 24198614 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 686503661 # Number of instructions processed by rename
|
|
system.cpu.rename.SquashedInsts 13339375 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 9395545 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 2450716 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 1889859 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 1786281 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 830901474 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 3018793647 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 723833359 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 176777723 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 1544705 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 1534955 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 42254952 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 143502988 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 67972899 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 12881093 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 11309167 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 668070815 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 2978330 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 610220228 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 5852709 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 122637533 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 318907162 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 698 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 463657706 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.316101 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.101419 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 147083310 31.72% 31.72% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 100037180 21.58% 53.30% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 146356248 31.57% 84.86% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 63253795 13.64% 98.51% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 6926698 1.49% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 475 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 463657706 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 71297182 52.75% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 31 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.75% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 44549866 32.96% 85.71% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 19309097 14.29% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 413143881 67.70% 67.70% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 351753 0.06% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 134202503 21.99% 89.75% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 62522088 10.25% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 610220228 # Type of FU issued
|
|
system.cpu.iq.rate 1.313932 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 135156176 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.221488 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 1825106754 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 793714763 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 594959628 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 745376227 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 7281483 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 27618232 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 25000 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 28827 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 11112422 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 224691 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 19267 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 6980725 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 22383279 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 635884 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 672535669 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 143502988 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 67972899 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 1489788 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 251092 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 252064 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 28827 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 3821462 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 3734064 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 7555526 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 599376603 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 129568443 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 10843625 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 1486524 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 190520911 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 131371292 # Number of branches executed
|
|
system.cpu.iew.exec_stores 60952468 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.290583 # Inst execution rate
|
|
system.cpu.iew.wb_sent 596255942 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 594959644 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 349870966 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 570295631 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.281072 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.613491 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 109920418 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 6954584 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 446560356 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.228714 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.894004 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 218012124 48.82% 48.82% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 116021741 25.98% 74.80% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 43540177 9.75% 84.55% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 23444560 5.25% 89.80% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 10920781 2.45% 92.25% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 8059552 1.80% 94.05% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 8487825 1.90% 95.95% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 4237549 0.95% 96.90% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 13836047 3.10% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 446560356 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 506581607 # Number of instructions committed
|
|
system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 172745233 # Number of memory references committed
|
|
system.cpu.commit.loads 115884756 # Number of loads committed
|
|
system.cpu.commit.membars 1488542 # Number of memory barriers committed
|
|
system.cpu.commit.branches 121548301 # Number of branches committed
|
|
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 448454354 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 375610373 68.46% 68.46% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 13836047 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 1091332417 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 1334357175 # The number of ROB writes
|
|
system.cpu.timesIdled 13678 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 765405 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 505237723 # Number of Instructions Simulated
|
|
system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.919217 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.919217 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.087882 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.087882 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 611063177 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 328106532 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
|
|
system.cpu.cc_regfile_reads 2170100255 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 376532879 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 217961412 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 2823114 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.633158 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 169651956 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2823626 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 60.083012 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 496259500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.633158 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999284 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999284 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 356228622 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 356228622 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 114681272 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 114681272 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 51990753 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 51990753 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 2786 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 2786 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488557 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 1488557 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 166672025 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 166672025 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 166674811 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 166674811 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 4801959 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 4801959 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 2248553 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 2248553 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 7050512 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 7050512 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 7050523 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 7050523 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 53499385357 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 53499385357 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 17165986851 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 17165986851 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1002500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 1002500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 70665372208 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 70665372208 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 70665372208 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 70665372208 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 119483231 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 119483231 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2797 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 2797 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488623 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 1488623 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 173722537 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 173722537 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 173725334 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 173725334 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040189 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.040189 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041456 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.041456 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003933 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.003933 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.040585 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.040585 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.040584 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.040584 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11141.158297 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 11141.158297 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7634.237152 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 7634.237152 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15189.393939 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15189.393939 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 10022.729159 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 10022.729159 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 10022.713522 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 10022.713522 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 454984 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 10035 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 45.339711 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 2354028 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 2354028 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2498261 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 2498261 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728610 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 1728610 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 4226871 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 4226871 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 4226871 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 4226871 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303698 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 2303698 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519943 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 519943 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2823641 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2823641 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2823651 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2823651 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25499562714 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 25499562714 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4017408221 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4017408221 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 706750 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 706750 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29516970935 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 29516970935 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29517677685 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 29517677685 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019281 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019281 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003575 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003575 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016254 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.016254 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016254 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.016254 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11068.969420 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11068.969420 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7726.631998 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7726.631998 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70675 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70675 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10453.514075 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 10453.514075 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10453.727350 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 10453.727350 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 73454 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 465.665769 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 236580046 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 73966 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 3198.497228 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 114499459250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 465.665769 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.909503 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.909503 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 473397028 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 473397028 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 236580046 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 236580046 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 236580046 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 236580046 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 236580046 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 236580046 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 81472 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 81472 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 81472 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 81472 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 81472 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 81472 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1465585914 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 1465585914 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 1465585914 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 1465585914 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 1465585914 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 1465585914 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 236661518 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 236661518 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 236661518 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 236661518 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 236661518 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 236661518 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000344 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000344 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000344 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000344 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000344 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000344 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17988.829463 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 17988.829463 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 17988.829463 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 17988.829463 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 17988.829463 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 17988.829463 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 164374 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 692 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 6271 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 26.211768 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 138.400000 # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7479 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 7479 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 7479 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 7479 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 7479 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 7479 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 73993 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 73993 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 73993 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 73993 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 73993 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 73993 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1129183847 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 1129183847 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1129183847 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 1129183847 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1129183847 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 1129183847 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15260.684754 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15260.684754 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15260.684754 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 15260.684754 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15260.684754 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 15260.684754 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 8509131 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.pfIdentified 8512942 # number of prefetch candidates identified
|
|
system.cpu.l2cache.prefetcher.pfBufferHit 2237 # number of redundant prefetches already in prefetch queue
|
|
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu.l2cache.prefetcher.pfSpanPage 743602 # number of prefetches not generated due to page crossing
|
|
system.cpu.l2cache.tags.replacements 401614 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 15413.386139 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 4559849 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 417953 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 10.909956 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 34584601500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 8474.787715 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 477.139723 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 4908.892257 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1552.566443 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.517260 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.029122 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.299615 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.094761 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.940758 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1022 1129 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15210 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 49 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 259 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 821 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1536 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10030 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3283 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.068909 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.928345 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 84965966 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 84965966 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 63311 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 2156931 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2220242 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 2354028 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 2354028 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 516650 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 516650 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 63311 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 2673581 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2736892 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 63311 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 2673581 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2736892 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 10651 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 144961 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 155612 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 5084 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 5084 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 10651 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 150045 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 160696 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 10651 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 150045 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 160696 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 711026986 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10160623428 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 10871650414 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 411274728 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 411274728 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 711026986 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 10571898156 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 11282925142 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 711026986 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 10571898156 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 11282925142 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 73962 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 2301892 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2375854 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 2354028 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 2354028 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 25 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 25 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 521734 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 521734 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 73962 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2823626 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2897588 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 73962 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2823626 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2897588 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.144006 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.062975 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.065497 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.080000 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.080000 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009744 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.009744 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.144006 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.053139 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.055459 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.144006 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.053139 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.055459 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66756.829030 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70092.117383 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69863.830643 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80895.894571 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80895.894571 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66756.829030 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70458.183585 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 70212.856213 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66756.829030 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70458.183585 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 70212.856213 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 292638 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 292638 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4068 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 4076 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1399 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::total 1399 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 5467 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 5475 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 5467 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 5475 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10643 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 140893 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 151536 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 275229 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::total 275229 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3685 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 3685 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 10643 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 144578 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 155221 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10643 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 144578 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 275229 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 430450 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 619626514 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8627975760 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9247602274 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18094630257 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18094630257 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 12002 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 12002 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 229963510 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 229963510 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 619626514 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8857939270 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 9477565784 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 619626514 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8857939270 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18094630257 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 27572196041 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.061207 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063782 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.080000 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.080000 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007063 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007063 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.051203 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.053569 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.051203 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.148555 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58219.159448 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61237.788677 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61025.777861 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 65743.908734 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62405.294437 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62405.294437 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61058.528060 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64054.352517 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2375885 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2375884 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 2354028 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFReq 335698 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 25 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 25 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 521734 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 521734 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 147954 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8001330 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 8149284 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733504 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331369856 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 336103360 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 335729 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 5587370 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 5.060082 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.237638 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::5 5251672 93.99% 93.99% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::6 335698 6.01% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 5587370 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 4979864499 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 112728958 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 4257992809 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadReq 408974 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 408974 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 292638 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 3 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
|
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system.membus.trans_dist::ReadExReq 3684 # Transaction distribution
|
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system.membus.trans_dist::ReadExResp 3684 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1117960 # Packet count per connected master and slave (bytes)
|
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system.membus.pkt_count::total 1117960 # Packet count per connected master and slave (bytes)
|
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system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45138944 # Cumulative packet size per connected master and slave (bytes)
|
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system.membus.pkt_size::total 45138944 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 705299 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 705299 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 705299 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 3281426491 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 3862639706 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 1.7 # Layer utilization (%)
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|
|
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---------- End Simulation Statistics ----------
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