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gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
Andreas Hansson df8df4fd0a stats: Bump stats for decoder, TLB, prefetcher and DRAM changes 
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
2014-12-23 09:31:20 -05:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.363671 # Number of seconds simulated
sim_ticks 2363670998000 # Number of ticks simulated
final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1113267 # Simulator instruction rate (inst/s)
host_op_rate 1199701 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1710076181 # Simulator tick rate (ticks/s)
host_mem_usage 309628 # Number of bytes of host memory used
host_seconds 1382.20 # Real time elapsed on the host
sim_insts 1538759601 # Number of instructions simulated
sim_ops 1658228914 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory
system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory
system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 16679 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 53020117 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 53036796 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 16679 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 16679 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 27542188 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 27542188 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 27542188 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 4727341996 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1538759601 # Number of instructions committed
system.cpu.committedOps 1658228914 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
system.cpu.num_func_calls 27330256 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls
system.cpu.num_int_insts 1477900422 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
system.cpu.num_int_register_reads 2601860372 # number of times the integer registers were read
system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu.num_cc_register_reads 6356387675 # number of times the CC registers were read
system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
system.cpu.num_mem_refs 633153380 # number of memory refs
system.cpu.num_load_insts 458306334 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
system.cpu.num_busy_cycles 4727341995.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
system.cpu.Branches 213462426 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction
system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction
system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1664032480 # Class of executed instruction
system.cpu.dcache.tags.replacements 9111140 # number of replacements
system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits
system.cpu.dcache.overall_hits::total 618379947 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency
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system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24708000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336506000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 78361214000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24708000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336506000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 78361214000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::5 12813292 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
system.membus.trans_dist::ReadReq 1177898 # Transaction distribution
system.membus.trans_dist::ReadResp 1177898 # Transaction distribution
system.membus.trans_dist::Writeback 1017198 # Transaction distribution
system.membus.trans_dist::ReadExReq 780876 # Transaction distribution
system.membus.trans_dist::ReadExResp 780876 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 2975972 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 2975972 # Request fanout histogram
system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
---------- End Simulation Statistics ----------
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