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gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt

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---------- Begin Simulation Statistics ----------
sim_seconds 0.000111 # Number of seconds simulated
sim_ticks 110872500 # Number of ticks simulated
final_tick 110872500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 118027 # Simulator instruction rate (inst/s)
host_op_rate 118027 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 12557410 # Simulator tick rate (ticks/s)
host_mem_usage 289008 # Number of bytes of host memory used
host_seconds 8.83 # Real time elapsed on the host
sim_insts 1042088 # Number of instructions simulated
sim_ops 1042088 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 4608 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.inst 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::total 42176 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 4608 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu3.inst 448 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 72 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.inst 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::total 659 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu0.inst 205497305 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 96976257 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 5772396 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 7504115 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 41561253 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 11544792 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.inst 4040677 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3.data 7504115 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 380400911 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 205497305 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 5772396 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 41561253 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu3.inst 4040677 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 256871632 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 205497305 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 96976257 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 5772396 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 7504115 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 41561253 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 11544792 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.inst 4040677 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 7504115 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 380400911 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 660 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 660 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 42240 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 42240 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 77 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 115 # Per bank write bursts
system.physmem.perBankRdBursts::1 39 # Per bank write bursts
system.physmem.perBankRdBursts::2 29 # Per bank write bursts
system.physmem.perBankRdBursts::3 60 # Per bank write bursts
system.physmem.perBankRdBursts::4 65 # Per bank write bursts
system.physmem.perBankRdBursts::5 27 # Per bank write bursts
system.physmem.perBankRdBursts::6 18 # Per bank write bursts
system.physmem.perBankRdBursts::7 24 # Per bank write bursts
system.physmem.perBankRdBursts::8 7 # Per bank write bursts
system.physmem.perBankRdBursts::9 28 # Per bank write bursts
system.physmem.perBankRdBursts::10 23 # Per bank write bursts
system.physmem.perBankRdBursts::11 12 # Per bank write bursts
system.physmem.perBankRdBursts::12 60 # Per bank write bursts
system.physmem.perBankRdBursts::13 38 # Per bank write bursts
system.physmem.perBankRdBursts::14 17 # Per bank write bursts
system.physmem.perBankRdBursts::15 98 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 110844500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 660 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 403 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 194 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 275.027027 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 186.656156 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 254.302887 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 45 30.41% 30.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 43 29.05% 59.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 21 14.19% 73.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 12 8.11% 81.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 10 6.76% 88.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 5 3.38% 91.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 5 3.38% 95.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1 0.68% 95.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 6 4.05% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation
system.physmem.totQLat 5597750 # Total ticks spent queuing
system.physmem.totMemAccLat 17972750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 3300000 # Total ticks spent in databus transfers
system.physmem.avgQLat 8481.44 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 27231.44 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 380.98 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 380.98 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.98 # Data bus utilization in percentage
system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 505 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 76.52 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 167946.21 # Average gap between requests
system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 48028250 # Time in different power states
system.physmem.memoryStateTime::REF 3640000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 57613000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 380400911 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 529 # Transaction distribution
system.membus.trans_dist::ReadResp 528 # Transaction distribution
system.membus.trans_dist::UpgradeReq 287 # Transaction distribution
system.membus.trans_dist::UpgradeResp 77 # Transaction distribution
system.membus.trans_dist::ReadExReq 163 # Transaction distribution
system.membus.trans_dist::ReadExResp 131 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1715 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 1715 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 42176 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 42176 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 42176 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 925500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
system.membus.respLayer1.occupancy 6302174 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 5.7 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 0 # number of replacements
system.l2c.tags.tagsinuse 417.213115 # Cycle average of tags in use
system.l2c.tags.total_refs 1443 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 526 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.743346 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 0.799585 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 285.091922 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 58.421534 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 7.040102 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 0.695019 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 55.399606 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 5.410902 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst 3.621924 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.data 0.732522 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.004350 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.000891 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.000107 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.000845 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.000083 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst 0.000055 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.006366 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 526 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 179 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.008026 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 18244 # Number of tag accesses
system.l2c.tags.data_accesses 18244 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 413 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 349 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.inst 420 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1443 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
system.l2c.Writeback_hits::total 1 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.inst 229 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 413 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 349 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.inst 420 # number of demand (read+write) hits
system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
system.l2c.demand_hits::total 1443 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 229 # number of overall hits
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
system.l2c.overall_hits::cpu1.inst 413 # number of overall hits
system.l2c.overall_hits::cpu1.data 11 # number of overall hits
system.l2c.overall_hits::cpu2.inst 349 # number of overall hits
system.l2c.overall_hits::cpu2.data 5 # number of overall hits
system.l2c.overall_hits::cpu3.inst 420 # number of overall hits
system.l2c.overall_hits::cpu3.data 11 # number of overall hits
system.l2c.overall_hits::total 1443 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 359 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 76 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.inst 10 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
system.l2c.ReadReq_misses::total 543 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.inst 359 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 15 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 76 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.inst 10 # number of demand (read+write) misses
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
system.l2c.demand_misses::total 674 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.inst 359 # number of overall misses
system.l2c.overall_misses::cpu0.data 168 # number of overall misses
system.l2c.overall_misses::cpu1.inst 15 # number of overall misses
system.l2c.overall_misses::cpu1.data 13 # number of overall misses
system.l2c.overall_misses::cpu2.inst 76 # number of overall misses
system.l2c.overall_misses::cpu2.data 20 # number of overall misses
system.l2c.overall_misses::cpu3.inst 10 # number of overall misses
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
system.l2c.overall_misses::total 674 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0.inst 24533250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.data 5569000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 1122250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 74500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 5286500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 495250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.inst 658250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3.data 74500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 37813500 # number of ReadReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 6780000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 852250 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 1087000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3.data 943000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 9662250 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0.inst 24533250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 12349000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 1122250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 926750 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 5286500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 1582250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.inst 658250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3.data 1017500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 47475750 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.inst 24533250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 12349000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 1122250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 926750 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 5286500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 1582250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.inst 658250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3.data 1017500 # number of overall miss cycles
system.l2c.overall_miss_latency::total 47475750 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 428 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 425 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.inst 430 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 80 # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.inst 588 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 428 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 425 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.inst 430 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2117 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 588 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 428 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 425 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.inst 430 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2117 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.610544 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.035047 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.178824 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.inst 0.023256 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.273414 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.962500 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.inst 0.610544 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.035047 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.178824 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.inst 0.023256 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.318375 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.inst 0.610544 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.035047 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.178824 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.inst 0.023256 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.318375 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68337.743733 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.data 75256.756757 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74816.666667 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 74500 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 69559.210526 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 70750 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 65825 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3.data 74500 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 69638.121547 # average ReadReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 72127.659574 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 71020.833333 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 83615.384615 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 78583.333333 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 73757.633588 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 68337.743733 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 73505.952381 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 74816.666667 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 69559.210526 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.inst 65825 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3.data 78269.230769 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 70438.798220 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 68337.743733 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 73505.952381 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 74816.666667 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 71288.461538 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 69559.210526 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 79112.500000 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.inst 65825 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3.data 78269.230769 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 70438.798220 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.inst 4 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst 4 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst 4 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0.inst 357 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 10 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst 72 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.inst 7 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 529 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 19 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst 357 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 10 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 72 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.inst 7 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 660 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst 357 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 10 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 72 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.inst 7 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 660 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 19962500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 4657000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 698750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4160750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 408750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 431250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 30444000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 220022 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 199518 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 160016 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200020 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 779576 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5606500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 701750 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 928000 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 792500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 8028750 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst 19962500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data 10263500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 698750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 764250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 4160750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 1336750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.inst 431250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3.data 855000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 38472750 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst 19962500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data 10263500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 698750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 764250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 4160750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 1336750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.inst 431250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3.data 855000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 38472750 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.169412 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.016279 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.266365 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.962500 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.169412 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.016279 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.023364 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.169412 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.016279 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62932.432432 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69875 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 58392.857143 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 57550.094518 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10500.947368 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10124.363636 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59643.617021 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58479.166667 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71384.615385 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 66041.666667 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 61288.167939 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61092.261905 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69875 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 65769.230769 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 58292.045455 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55917.366947 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61092.261905 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69875 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58788.461538 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 57788.194444 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66837.500000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61607.142857 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 65769.230769 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 58292.045455 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.toL2Bus.throughput 1690157613 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 2536 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2535 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 392 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 392 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1175 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 587 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 850 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 371 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 860 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 356 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 5415 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 37568 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 27392 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 27200 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 27520 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 135488 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 135488 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 51904 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 1624477 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 2708498 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 1467012 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 1928746 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 1148249 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 1927493 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%)
system.toL2Bus.respLayer5.occupancy 1209237 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 1936745 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 1.7 # Layer utilization (%)
system.toL2Bus.respLayer7.occupancy 1133003 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 1.0 # Layer utilization (%)
system.cpu0.branchPred.lookups 82981 # Number of BP lookups
system.cpu0.branchPred.condPredicted 80783 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 80310 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 78265 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 97.453617 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions.
system.cpu0.workload.num_syscalls 89 # Number of system calls
system.cpu0.numCycles 221746 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 17234 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 492474 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 82981 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 78777 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 161662 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 3811 # Number of cycles fetch has spent squashing
system.cpu0.fetch.BlockedCycles 13862 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 1512 # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 492 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.rateDist::samples 196720 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 2.503426 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 2.215057 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 35058 17.82% 17.82% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 80078 40.71% 58.53% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 578 0.29% 58.82% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 973 0.49% 59.32% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::5 76182 38.73% 98.28% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::6 570 0.29% 98.57% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::8 2455 1.25% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 196720 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.374216 # Number of branch fetches per cycle
system.cpu0.fetch.rate 2.220892 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 17819 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 15483 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 160693 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 280 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 2445 # Number of cycles decode is squashing
system.cpu0.decode.DecodedInsts 489648 # Number of instructions handled by decode
system.cpu0.rename.SquashCycles 2445 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 18474 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 866 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 14003 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 160341 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 591 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 486805 # Number of instructions processed by rename
system.cpu0.rename.LSQFullEvents 216 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RenamedOperands 332880 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 970801 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 733282 # Number of integer rename lookups
system.cpu0.rename.CommittedMaps 319911 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 12969 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 866 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 886 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 3624 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 155743 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 78707 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 75959 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 75775 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 407094 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 910 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 404367 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 10771 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 9755 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 351 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 196720 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 2.055546 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.097437 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 34036 17.30% 17.30% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 4955 2.52% 19.82% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 77877 39.59% 59.41% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 77259 39.27% 98.68% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1573 0.80% 99.48% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 652 0.33% 99.81% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 264 0.13% 99.95% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 196720 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 57 25.79% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.79% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 52 23.53% 49.32% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 112 50.68% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 170970 42.28% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.28% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 155279 38.40% 80.68% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 78118 19.32% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 404367 # Type of FU issued
system.cpu0.iq.rate 1.823559 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 221 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.000547 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 1005807 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 418829 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 402541 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 404588 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 75486 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 2198 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 1428 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 2445 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 400 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 484514 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 312 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 155743 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 78707 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 798 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 343 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 1449 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 403298 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 154949 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1069 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 76510 # number of nop insts executed
system.cpu0.iew.exec_refs 232965 # number of memory reference insts executed
system.cpu0.iew.exec_branches 80120 # Number of branches executed
system.cpu0.iew.exec_stores 78016 # Number of stores executed
system.cpu0.iew.exec_rate 1.818739 # Inst execution rate
system.cpu0.iew.wb_sent 402871 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 402541 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 238524 # num instructions producing a value
system.cpu0.iew.wb_consumers 240975 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 1.815325 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.989829 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 12269 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 194275 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 2.430668 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 2.136401 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 34469 17.74% 17.74% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 79913 41.13% 58.88% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 2377 1.22% 60.10% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 686 0.35% 60.45% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 532 0.27% 60.73% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 75283 38.75% 99.48% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 460 0.24% 99.71% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.84% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 305 0.16% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 194275 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 472218 # Number of instructions committed
system.cpu0.commit.committedOps 472218 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 230824 # Number of memory references committed
system.cpu0.commit.loads 153545 # Number of loads committed
system.cpu0.commit.membars 84 # Number of memory barriers committed
system.cpu0.commit.branches 79166 # Number of branches committed
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 318242 # Number of committed integer instructions.
system.cpu0.commit.function_calls 223 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 75898 16.07% 16.07% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 165412 35.03% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.10% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 153629 32.53% 83.63% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 77279 16.37% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 472218 # Class of committed instruction
system.cpu0.commit.bw_lim_events 305 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 677296 # The number of ROB reads
system.cpu0.rob.rob_writes 971436 # The number of ROB writes
system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 25026 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts 396236 # Number of Instructions Simulated
system.cpu0.committedOps 396236 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 396236 # Number of Instructions Simulated
system.cpu0.cpi 0.559631 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 0.559631 # CPI: Total CPI of All Threads
system.cpu0.ipc 1.786891 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 1.786891 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 721496 # number of integer regfile reads
system.cpu0.int_regfile_writes 325166 # number of integer regfile writes
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
system.cpu0.misc_regfile_reads 234788 # number of misc regfile reads
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
system.cpu0.icache.tags.replacements 297 # number of replacements
system.cpu0.icache.tags.tagsinuse 241.323737 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 5079 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 587 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 8.652470 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.323737 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471335 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.471335 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 290 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.566406 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 6422 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 6422 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 5079 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 5079 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 5079 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 5079 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 5079 # number of overall hits
system.cpu0.icache.overall_hits::total 5079 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 756 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 756 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 756 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 756 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 756 # number of overall misses
system.cpu0.icache.overall_misses::total 756 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 35655495 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 35655495 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 35655495 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 35655495 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 35655495 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 35655495 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 5835 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 5835 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 5835 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 5835 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 5835 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 5835 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.129563 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.129563 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.129563 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.129563 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.129563 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.129563 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47163.353175 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 47163.353175 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47163.353175 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 47163.353175 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47163.353175 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 47163.353175 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 168 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 168 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 168 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 168 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 588 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 588 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27420002 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 27420002 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27420002 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 27420002 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27420002 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 27420002 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100771 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.100771 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100771 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.100771 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 46632.656463 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 46632.656463 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 46632.656463 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 46632.656463 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 2 # number of replacements
system.cpu0.dcache.tags.tagsinuse 142.026535 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 155594 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 915.258824 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.026535 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.277396 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.277396 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 627036 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 627036 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 78986 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 78986 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 76692 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 76692 # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits
system.cpu0.dcache.demand_hits::cpu0.data 155678 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 155678 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 155678 # number of overall hits
system.cpu0.dcache.overall_hits::total 155678 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 416 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 416 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 545 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses
system.cpu0.dcache.demand_misses::cpu0.data 961 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 961 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 961 # number of overall misses
system.cpu0.dcache.overall_misses::total 961 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13375931 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 13375931 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32683256 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 32683256 # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 404750 # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total 404750 # number of SwapReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 46059187 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 46059187 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 46059187 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 46059187 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 79402 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 79402 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 77237 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 77237 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 156639 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 156639 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 156639 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 156639 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005239 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.005239 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007056 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.007056 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006135 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.006135 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006135 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.006135 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32153.680288 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 32153.680288 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 59969.277064 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 59969.277064 # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19273.809524 # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 19273.809524 # average SwapReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47928.394381 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 47928.394381 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47928.394381 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 47928.394381 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 512 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 24.380952 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 228 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 228 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 598 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 598 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 598 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 598 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 363 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 363 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 363 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 363 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6192510 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6192510 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7258228 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7258228 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 361250 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 361250 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13450738 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 13450738 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13450738 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 13450738 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002368 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002368 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002266 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002266 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002317 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.002317 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002317 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002317 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32938.882979 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32938.882979 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41475.588571 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41475.588571 # average WriteReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17202.380952 # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17202.380952 # average SwapReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 37054.374656 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37054.374656 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 37054.374656 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 37054.374656 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.branchPred.lookups 49222 # Number of BP lookups
system.cpu1.branchPred.condPredicted 46474 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 1275 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 43117 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 42310 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 98.128348 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 644 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu1.numCycles 177641 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 30689 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 271480 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 49222 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 42954 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 98036 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3712 # Number of cycles fetch has spent squashing
system.cpu1.fetch.BlockedCycles 35816 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles 7751 # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles 775 # Number of stall cycles due to pending traps
system.cpu1.fetch.CacheLines 22336 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 259 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.rateDist::samples 175432 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.547494 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.089471 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 77396 44.12% 44.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 50499 28.79% 72.90% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 7414 4.23% 77.13% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 3189 1.82% 78.95% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::4 704 0.40% 79.35% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::5 30975 17.66% 97.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::6 1193 0.68% 97.68% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::7 759 0.43% 98.12% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::8 3303 1.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 175432 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.277087 # Number of branch fetches per cycle
system.cpu1.fetch.rate 1.528251 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 37161 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 30981 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 90858 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 6321 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 2360 # Number of cycles decode is squashing
system.cpu1.decode.DecodedInsts 267812 # Number of instructions handled by decode
system.cpu1.rename.SquashCycles 2360 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 37844 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 18525 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 11702 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 84806 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 12444 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 265497 # Number of instructions processed by rename
system.cpu1.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full
system.cpu1.rename.RenamedOperands 184374 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 502466 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 391647 # Number of integer rename lookups
system.cpu1.rename.CommittedMaps 171546 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 12828 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 1100 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 1220 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 15168 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 73767 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 34233 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 35724 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 29188 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 218285 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 7630 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 221655 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 99 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 10737 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 10712 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 591 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 175432 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 1.263481 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.299438 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 74808 42.64% 42.64% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 26276 14.98% 57.62% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 34476 19.65% 77.27% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 35104 20.01% 97.28% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 3248 1.85% 99.13% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 1161 0.66% 99.80% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 252 0.14% 99.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 175432 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 12 4.51% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 4.51% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 44 16.54% 21.05% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 210 78.95% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 108760 49.07% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.07% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 79356 35.80% 84.87% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 33539 15.13% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 221655 # Type of FU issued
system.cpu1.iq.rate 1.247769 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 266 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.001200 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 619107 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 236695 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 219827 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 221921 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 28930 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 2394 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 1444 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 2360 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 686 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 42 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 262565 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 349 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 73767 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 34233 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 1056 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 467 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 918 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 220479 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 72759 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 36650 # number of nop insts executed
system.cpu1.iew.exec_refs 106217 # number of memory reference insts executed
system.cpu1.iew.exec_branches 45894 # Number of branches executed
system.cpu1.iew.exec_stores 33458 # Number of stores executed
system.cpu1.iew.exec_rate 1.241149 # Inst execution rate
system.cpu1.iew.wb_sent 220112 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 219827 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 122951 # num instructions producing a value
system.cpu1.iew.wb_consumers 127610 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 1.237479 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.963490 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 12326 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 7039 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 1275 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 165321 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 1.513546 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.970448 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 73866 44.68% 44.68% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 44045 26.64% 71.32% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 6103 3.69% 75.01% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 7953 4.81% 79.82% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1564 0.95% 80.77% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 29501 17.84% 98.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 477 0.29% 98.90% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 1008 0.61% 99.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 804 0.49% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 165321 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 250221 # Number of instructions committed
system.cpu1.commit.committedOps 250221 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 104162 # Number of memory references committed
system.cpu1.commit.loads 71373 # Number of loads committed
system.cpu1.commit.membars 6322 # Number of memory barriers committed
system.cpu1.commit.branches 45072 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 171353 # Number of committed integer instructions.
system.cpu1.commit.function_calls 322 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 35859 14.33% 14.33% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 103878 41.51% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.85% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 77695 31.05% 86.90% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 32789 13.10% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 250221 # Class of committed instruction
system.cpu1.commit.bw_lim_events 804 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 426477 # The number of ROB reads
system.cpu1.rob.rob_writes 527460 # The number of ROB writes
system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 2209 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 44103 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 208040 # Number of Instructions Simulated
system.cpu1.committedOps 208040 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 208040 # Number of Instructions Simulated
system.cpu1.cpi 0.853879 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 0.853879 # CPI: Total CPI of All Threads
system.cpu1.ipc 1.171126 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 1.171126 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 377205 # number of integer regfile reads
system.cpu1.int_regfile_writes 176304 # number of integer regfile writes
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
system.cpu1.misc_regfile_reads 107775 # number of misc regfile reads
system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
system.cpu1.icache.tags.replacements 318 # number of replacements
system.cpu1.icache.tags.tagsinuse 76.769709 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 21861 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 428 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 51.077103 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.769709 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.149941 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.149941 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 22764 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 22764 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 21861 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 21861 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 21861 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 21861 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 21861 # number of overall hits
system.cpu1.icache.overall_hits::total 21861 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 475 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 475 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 475 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 475 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 475 # number of overall misses
system.cpu1.icache.overall_misses::total 475 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7146245 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 7146245 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 7146245 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 7146245 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 7146245 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 7146245 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 22336 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 22336 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 22336 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 22336 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 22336 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 22336 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021266 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.021266 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021266 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.021266 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021266 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.021266 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15044.726316 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 15044.726316 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15044.726316 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 15044.726316 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15044.726316 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 15044.726316 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 26 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 13 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 47 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 47 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 47 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 47 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 47 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 47 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 428 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 428 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 428 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 428 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5694254 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5694254 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5694254 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 5694254 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5694254 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 5694254 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019162 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.019162 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019162 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.019162 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13304.331776 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 13304.331776 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13304.331776 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 13304.331776 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.tags.replacements 0 # number of replacements
system.cpu1.dcache.tags.tagsinuse 23.645460 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 38791 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 1385.392857 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.645460 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.046183 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.046183 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 306653 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 306653 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 43477 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 43477 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 32586 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 32586 # number of WriteReq hits
system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
system.cpu1.dcache.demand_hits::cpu1.data 76063 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 76063 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 76063 # number of overall hits
system.cpu1.dcache.overall_hits::total 76063 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 336 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 336 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 132 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 132 # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses
system.cpu1.dcache.demand_misses::cpu1.data 468 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 468 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 468 # number of overall misses
system.cpu1.dcache.overall_misses::total 468 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4177635 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 4177635 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2763761 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 2763761 # number of WriteReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 521507 # number of SwapReq miss cycles
system.cpu1.dcache.SwapReq_miss_latency::total 521507 # number of SwapReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 6941396 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 6941396 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 6941396 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 6941396 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 43813 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 43813 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 32718 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 32718 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 76531 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 76531 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 76531 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 76531 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.007669 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.007669 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004034 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.004034 # miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006115 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.006115 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006115 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.006115 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12433.437500 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 12433.437500 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20937.583333 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 20937.583333 # average WriteReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9149.245614 # average SwapReq miss latency
system.cpu1.dcache.SwapReq_avg_miss_latency::total 9149.245614 # average SwapReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14832.042735 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 14832.042735 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14832.042735 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 14832.042735 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 178 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 178 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 30 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 30 # number of WriteReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 208 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 208 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 208 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 208 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 158 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 158 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 102 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 260 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 260 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1076519 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1076519 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1313739 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1313739 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 407493 # number of SwapReq MSHR miss cycles
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 407493 # number of SwapReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2390258 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 2390258 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2390258 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 2390258 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003606 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003606 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003118 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003118 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.802817 # mshr miss rate for SwapReq accesses
system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003397 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.003397 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003397 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.003397 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 6813.411392 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 6813.411392 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12879.794118 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12879.794118 # average WriteReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7149 # average SwapReq mshr miss latency
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7149 # average SwapReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9193.300000 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9193.300000 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9193.300000 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9193.300000 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.branchPred.lookups 47728 # Number of BP lookups
system.cpu2.branchPred.condPredicted 45021 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 1300 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 41568 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 40861 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 98.299172 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 682 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu2.numCycles 177276 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 30843 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 263204 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 47728 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 41543 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 94904 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 3824 # Number of cycles fetch has spent squashing
system.cpu2.fetch.BlockedCycles 35041 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles 7749 # Number of stall cycles due to no active thread to fetch from
system.cpu2.fetch.PendingTrapStallCycles 807 # Number of stall cycles due to pending traps
system.cpu2.fetch.CacheLines 21784 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.rateDist::samples 171794 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.532091 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.088011 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 76890 44.76% 44.76% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 48833 28.43% 73.18% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 7151 4.16% 77.34% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 3183 1.85% 79.20% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 686 0.40% 79.60% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 29845 17.37% 96.97% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 1160 0.68% 97.64% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 777 0.45% 98.10% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 3269 1.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 171794 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.269230 # Number of branch fetches per cycle
system.cpu2.fetch.rate 1.484713 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 36742 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 30806 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 88081 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 5970 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 2446 # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts 259729 # Number of instructions handled by decode
system.cpu2.rename.SquashCycles 2446 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 37466 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 17718 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 12322 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 82351 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 11742 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 257457 # Number of instructions processed by rename
system.cpu2.rename.LSQFullEvents 21 # Number of times rename has blocked due to LSQ full
system.cpu2.rename.RenamedOperands 179534 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 487570 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 380512 # Number of integer rename lookups
system.cpu2.rename.CommittedMaps 166403 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 13131 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 1114 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 1238 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 14439 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 71183 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 33053 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 34319 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 28008 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 212034 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 7370 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 214866 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 11214 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 11199 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 171794 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.250719 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.303691 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 74486 43.36% 43.36% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 25336 14.75% 58.11% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 33280 19.37% 77.48% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 33902 19.73% 97.21% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 3243 1.89% 99.10% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 1160 0.68% 99.77% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 274 0.16% 99.93% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 171794 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 17 6.18% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.18% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 48 17.45% 23.64% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 210 76.36% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 106150 49.40% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.40% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 76361 35.54% 84.94% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 32355 15.06% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 214866 # Type of FU issued
system.cpu2.iq.rate 1.212042 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 275 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.001280 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 601907 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 230666 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 213047 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 215141 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 27720 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 2543 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 48 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 1469 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 2446 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 916 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 254607 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 365 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 71183 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 33053 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 1074 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 48 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 458 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 967 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 1425 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 213716 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 70082 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 1150 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 35203 # number of nop insts executed
system.cpu2.iew.exec_refs 102354 # number of memory reference insts executed
system.cpu2.iew.exec_branches 44387 # Number of branches executed
system.cpu2.iew.exec_stores 32272 # Number of stores executed
system.cpu2.iew.exec_rate 1.205555 # Inst execution rate
system.cpu2.iew.wb_sent 213334 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 213047 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 119124 # num instructions producing a value
system.cpu2.iew.wb_consumers 123829 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 1.201781 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.962004 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 12897 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 6722 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 1300 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 161599 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.495727 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.966465 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 73205 45.30% 45.30% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 42525 26.32% 71.62% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 6095 3.77% 75.39% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 7628 4.72% 80.11% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 1558 0.96% 81.07% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 28296 17.51% 98.58% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 469 0.29% 98.87% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 161599 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 241708 # Number of instructions committed
system.cpu2.commit.committedOps 241708 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 100224 # Number of memory references committed
system.cpu2.commit.loads 68640 # Number of loads committed
system.cpu2.commit.membars 6003 # Number of memory barriers committed
system.cpu2.commit.branches 43548 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 165890 # Number of committed integer instructions.
system.cpu2.commit.function_calls 322 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 34333 14.20% 14.20% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu 101148 41.85% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.05% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead 74643 30.88% 86.93% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite 31584 13.07% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total 241708 # Class of committed instruction
system.cpu2.commit.bw_lim_events 822 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 414795 # The number of ROB reads
system.cpu2.rob.rob_writes 511661 # The number of ROB writes
system.cpu2.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 5482 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 44468 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 201372 # Number of Instructions Simulated
system.cpu2.committedOps 201372 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 201372 # Number of Instructions Simulated
system.cpu2.cpi 0.880341 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 0.880341 # CPI: Total CPI of All Threads
system.cpu2.ipc 1.135924 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 1.135924 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 365782 # number of integer regfile reads
system.cpu2.int_regfile_writes 171355 # number of integer regfile writes
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
system.cpu2.misc_regfile_reads 103916 # number of misc regfile reads
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
system.cpu2.icache.tags.replacements 317 # number of replacements
system.cpu2.icache.tags.tagsinuse 82.236907 # Cycle average of tags in use
system.cpu2.icache.tags.total_refs 21297 # Total number of references to valid blocks.
system.cpu2.icache.tags.sampled_refs 425 # Sample count of references to valid blocks.
system.cpu2.icache.tags.avg_refs 50.110588 # Average number of references to valid blocks.
system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.tags.occ_blocks::cpu2.inst 82.236907 # Average occupied blocks per requestor
system.cpu2.icache.tags.occ_percent::cpu2.inst 0.160619 # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_percent::total 0.160619 # Average percentage of cache occupancy
system.cpu2.icache.tags.occ_task_id_blocks::1024 108 # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id
system.cpu2.icache.tags.occ_task_id_percent::1024 0.210938 # Percentage of cache occupancy per task id
system.cpu2.icache.tags.tag_accesses 22209 # Number of tag accesses
system.cpu2.icache.tags.data_accesses 22209 # Number of data accesses
system.cpu2.icache.ReadReq_hits::cpu2.inst 21297 # number of ReadReq hits
system.cpu2.icache.ReadReq_hits::total 21297 # number of ReadReq hits
system.cpu2.icache.demand_hits::cpu2.inst 21297 # number of demand (read+write) hits
system.cpu2.icache.demand_hits::total 21297 # number of demand (read+write) hits
system.cpu2.icache.overall_hits::cpu2.inst 21297 # number of overall hits
system.cpu2.icache.overall_hits::total 21297 # number of overall hits
system.cpu2.icache.ReadReq_misses::cpu2.inst 487 # number of ReadReq misses
system.cpu2.icache.ReadReq_misses::total 487 # number of ReadReq misses
system.cpu2.icache.demand_misses::cpu2.inst 487 # number of demand (read+write) misses
system.cpu2.icache.demand_misses::total 487 # number of demand (read+write) misses
system.cpu2.icache.overall_misses::cpu2.inst 487 # number of overall misses
system.cpu2.icache.overall_misses::total 487 # number of overall misses
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11521239 # number of ReadReq miss cycles
system.cpu2.icache.ReadReq_miss_latency::total 11521239 # number of ReadReq miss cycles
system.cpu2.icache.demand_miss_latency::cpu2.inst 11521239 # number of demand (read+write) miss cycles
system.cpu2.icache.demand_miss_latency::total 11521239 # number of demand (read+write) miss cycles
system.cpu2.icache.overall_miss_latency::cpu2.inst 11521239 # number of overall miss cycles
system.cpu2.icache.overall_miss_latency::total 11521239 # number of overall miss cycles
system.cpu2.icache.ReadReq_accesses::cpu2.inst 21784 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_accesses::total 21784 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.demand_accesses::cpu2.inst 21784 # number of demand (read+write) accesses
system.cpu2.icache.demand_accesses::total 21784 # number of demand (read+write) accesses
system.cpu2.icache.overall_accesses::cpu2.inst 21784 # number of overall (read+write) accesses
system.cpu2.icache.overall_accesses::total 21784 # number of overall (read+write) accesses
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.022356 # miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_miss_rate::total 0.022356 # miss rate for ReadReq accesses
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.022356 # miss rate for demand accesses
system.cpu2.icache.demand_miss_rate::total 0.022356 # miss rate for demand accesses
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.022356 # miss rate for overall accesses
system.cpu2.icache.overall_miss_rate::total 0.022356 # miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23657.574949 # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_miss_latency::total 23657.574949 # average ReadReq miss latency
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23657.574949 # average overall miss latency
system.cpu2.icache.demand_avg_miss_latency::total 23657.574949 # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23657.574949 # average overall miss latency
system.cpu2.icache.overall_avg_miss_latency::total 23657.574949 # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_mshrs 85 # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 62 # number of ReadReq MSHR hits
system.cpu2.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits
system.cpu2.icache.demand_mshr_hits::cpu2.inst 62 # number of demand (read+write) MSHR hits
system.cpu2.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits
system.cpu2.icache.overall_mshr_hits::cpu2.inst 62 # number of overall MSHR hits
system.cpu2.icache.overall_mshr_hits::total 62 # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 425 # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst 425 # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst 425 # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total 425 # number of overall MSHR misses
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 9226007 # number of ReadReq MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_latency::total 9226007 # number of ReadReq MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 9226007 # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.demand_mshr_miss_latency::total 9226007 # number of demand (read+write) MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 9226007 # number of overall MSHR miss cycles
system.cpu2.icache.overall_mshr_miss_latency::total 9226007 # number of overall MSHR miss cycles
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for ReadReq accesses
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019510 # mshr miss rate for ReadReq accesses
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for demand accesses
system.cpu2.icache.demand_mshr_miss_rate::total 0.019510 # mshr miss rate for demand accesses
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019510 # mshr miss rate for overall accesses
system.cpu2.icache.overall_mshr_miss_rate::total 0.019510 # mshr miss rate for overall accesses
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average ReadReq mshr miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21708.251765 # average ReadReq mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average overall mshr miss latency
system.cpu2.icache.demand_avg_mshr_miss_latency::total 21708.251765 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21708.251765 # average overall mshr miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency::total 21708.251765 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.tags.replacements 0 # number of replacements
system.cpu2.dcache.tags.tagsinuse 26.169210 # Cycle average of tags in use
system.cpu2.dcache.tags.total_refs 37730 # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
system.cpu2.dcache.tags.avg_refs 1301.034483 # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.169210 # Average occupied blocks per requestor
system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051112 # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_percent::total 0.051112 # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
system.cpu2.dcache.tags.tag_accesses 295974 # Number of tag accesses
system.cpu2.dcache.tags.data_accesses 295974 # Number of data accesses
system.cpu2.dcache.ReadReq_hits::cpu2.data 42003 # number of ReadReq hits
system.cpu2.dcache.ReadReq_hits::total 42003 # number of ReadReq hits
system.cpu2.dcache.WriteReq_hits::cpu2.data 31371 # number of WriteReq hits
system.cpu2.dcache.WriteReq_hits::total 31371 # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits
system.cpu2.dcache.demand_hits::cpu2.data 73374 # number of demand (read+write) hits
system.cpu2.dcache.demand_hits::total 73374 # number of demand (read+write) hits
system.cpu2.dcache.overall_hits::cpu2.data 73374 # number of overall hits
system.cpu2.dcache.overall_hits::total 73374 # number of overall hits
system.cpu2.dcache.ReadReq_misses::cpu2.data 342 # number of ReadReq misses
system.cpu2.dcache.ReadReq_misses::total 342 # number of ReadReq misses
system.cpu2.dcache.WriteReq_misses::cpu2.data 140 # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total 140 # number of WriteReq misses
system.cpu2.dcache.SwapReq_misses::cpu2.data 59 # number of SwapReq misses
system.cpu2.dcache.SwapReq_misses::total 59 # number of SwapReq misses
system.cpu2.dcache.demand_misses::cpu2.data 482 # number of demand (read+write) misses
system.cpu2.dcache.demand_misses::total 482 # number of demand (read+write) misses
system.cpu2.dcache.overall_misses::cpu2.data 482 # number of overall misses
system.cpu2.dcache.overall_misses::total 482 # number of overall misses
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5435581 # number of ReadReq miss cycles
system.cpu2.dcache.ReadReq_miss_latency::total 5435581 # number of ReadReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3139010 # number of WriteReq miss cycles
system.cpu2.dcache.WriteReq_miss_latency::total 3139010 # number of WriteReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 574505 # number of SwapReq miss cycles
system.cpu2.dcache.SwapReq_miss_latency::total 574505 # number of SwapReq miss cycles
system.cpu2.dcache.demand_miss_latency::cpu2.data 8574591 # number of demand (read+write) miss cycles
system.cpu2.dcache.demand_miss_latency::total 8574591 # number of demand (read+write) miss cycles
system.cpu2.dcache.overall_miss_latency::cpu2.data 8574591 # number of overall miss cycles
system.cpu2.dcache.overall_miss_latency::total 8574591 # number of overall miss cycles
system.cpu2.dcache.ReadReq_accesses::cpu2.data 42345 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_accesses::total 42345 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::cpu2.data 31511 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.WriteReq_accesses::total 31511 # number of WriteReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses)
system.cpu2.dcache.demand_accesses::cpu2.data 73856 # number of demand (read+write) accesses
system.cpu2.dcache.demand_accesses::total 73856 # number of demand (read+write) accesses
system.cpu2.dcache.overall_accesses::cpu2.data 73856 # number of overall (read+write) accesses
system.cpu2.dcache.overall_accesses::total 73856 # number of overall (read+write) accesses
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.008077 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_miss_rate::total 0.008077 # miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004443 # miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_miss_rate::total 0.004443 # miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.808219 # miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_miss_rate::total 0.808219 # miss rate for SwapReq accesses
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.006526 # miss rate for demand accesses
system.cpu2.dcache.demand_miss_rate::total 0.006526 # miss rate for demand accesses
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.006526 # miss rate for overall accesses
system.cpu2.dcache.overall_miss_rate::total 0.006526 # miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 15893.511696 # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_miss_latency::total 15893.511696 # average ReadReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22421.500000 # average WriteReq miss latency
system.cpu2.dcache.WriteReq_avg_miss_latency::total 22421.500000 # average WriteReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9737.372881 # average SwapReq miss latency
system.cpu2.dcache.SwapReq_avg_miss_latency::total 9737.372881 # average SwapReq miss latency
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17789.607884 # average overall miss latency
system.cpu2.dcache.demand_avg_miss_latency::total 17789.607884 # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17789.607884 # average overall miss latency
system.cpu2.dcache.overall_avg_miss_latency::total 17789.607884 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 177 # number of ReadReq MSHR hits
system.cpu2.dcache.ReadReq_mshr_hits::total 177 # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
system.cpu2.dcache.demand_mshr_hits::cpu2.data 211 # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_hits::total 211 # number of demand (read+write) MSHR hits
system.cpu2.dcache.overall_mshr_hits::cpu2.data 211 # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_hits::total 211 # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 165 # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total 165 # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses
system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1515278 # number of ReadReq MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1515278 # number of ReadReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1527990 # number of WriteReq MSHR miss cycles
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1527990 # number of WriteReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 456495 # number of SwapReq MSHR miss cycles
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 456495 # number of SwapReq MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3043268 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_latency::total 3043268 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3043268 # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_latency::total 3043268 # number of overall MSHR miss cycles
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003897 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003897 # mshr miss rate for ReadReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003364 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003364 # mshr miss rate for WriteReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.808219 # mshr miss rate for SwapReq accesses
system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.808219 # mshr miss rate for SwapReq accesses
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003669 # mshr miss rate for demand accesses
system.cpu2.dcache.demand_mshr_miss_rate::total 0.003669 # mshr miss rate for demand accesses
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003669 # mshr miss rate for overall accesses
system.cpu2.dcache.overall_mshr_miss_rate::total 0.003669 # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9183.503030 # average ReadReq mshr miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9183.503030 # average ReadReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 14415 # average WriteReq mshr miss latency
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 14415 # average WriteReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7737.203390 # average SwapReq mshr miss latency
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7737.203390 # average SwapReq mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11229.771218 # average overall mshr miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11229.771218 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11229.771218 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11229.771218 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.branchPred.lookups 53964 # Number of BP lookups
system.cpu3.branchPred.condPredicted 51232 # Number of conditional branches predicted
system.cpu3.branchPred.condIncorrect 1265 # Number of conditional branches incorrect
system.cpu3.branchPred.BTBLookups 47874 # Number of BTB lookups
system.cpu3.branchPred.BTBHits 47117 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct 98.418766 # BTB Hit Percentage
system.cpu3.branchPred.usedRAS 645 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu3.numCycles 176930 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu3.fetch.icacheStallCycles 27837 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts 302665 # Number of instructions fetch has processed
system.cpu3.fetch.Branches 53964 # Number of branches that fetch encountered
system.cpu3.fetch.predictedBranches 47762 # Number of branches that fetch has predicted taken
system.cpu3.fetch.Cycles 106222 # Number of cycles fetch has run and was not squashing or blocked
system.cpu3.fetch.SquashCycles 3643 # Number of cycles fetch has spent squashing
system.cpu3.fetch.BlockedCycles 30631 # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles 7749 # Number of stall cycles due to no active thread to fetch from
system.cpu3.fetch.PendingTrapStallCycles 799 # Number of stall cycles due to pending traps
system.cpu3.fetch.CacheLines 19577 # Number of cache lines fetched
system.cpu3.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.rateDist::samples 175543 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::mean 1.724164 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::stdev 2.153360 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::0 69321 39.49% 39.49% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::1 53950 30.73% 70.22% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::2 6031 3.44% 73.66% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::3 3206 1.83% 75.48% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::4 696 0.40% 75.88% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::5 37091 21.13% 97.01% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 1217 0.69% 97.70% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::7 754 0.43% 98.13% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::8 3277 1.87% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::total 175543 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.branchRate 0.305002 # Number of branch fetches per cycle
system.cpu3.fetch.rate 1.710648 # Number of inst fetches per cycle
system.cpu3.decode.IdleCycles 32973 # Number of cycles decode is idle
system.cpu3.decode.BlockedCycles 27130 # Number of cycles decode is blocked
system.cpu3.decode.RunCycles 100348 # Number of cycles decode is running
system.cpu3.decode.UnblockCycles 5043 # Number of cycles decode is unblocking
system.cpu3.decode.SquashCycles 2300 # Number of cycles decode is squashing
system.cpu3.decode.DecodedInsts 299109 # Number of instructions handled by decode
system.cpu3.rename.SquashCycles 2300 # Number of cycles rename is squashing
system.cpu3.rename.IdleCycles 33648 # Number of cycles rename is idle
system.cpu3.rename.BlockCycles 14616 # Number of cycles rename is blocking
system.cpu3.rename.serializeStallCycles 11766 # count of cycles rename stalled for serializing inst
system.cpu3.rename.RunCycles 95589 # Number of cycles rename is running
system.cpu3.rename.UnblockCycles 9875 # Number of cycles rename is unblocking
system.cpu3.rename.RenamedInsts 296992 # Number of instructions processed by rename
system.cpu3.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
system.cpu3.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full
system.cpu3.rename.RenamedOperands 207702 # Number of destination operands rename has renamed
system.cpu3.rename.RenameLookups 570845 # Number of register rename lookups that rename has made
system.cpu3.rename.int_rename_lookups 442935 # Number of integer rename lookups
system.cpu3.rename.CommittedMaps 195079 # Number of HB maps that are committed
system.cpu3.rename.UndoneMaps 12623 # Number of HB maps that are undone due to squashing
system.cpu3.rename.serializingInsts 1101 # count of serializing insts renamed
system.cpu3.rename.tempSerializingInsts 1224 # count of temporary serializing insts renamed
system.cpu3.rename.skidInsts 12490 # count of insts added to the skid buffer
system.cpu3.memDep0.insertedLoads 84722 # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores 40383 # Number of stores inserted to the mem dependence unit.
system.cpu3.memDep0.conflictingLoads 40455 # Number of conflicting loads.
system.cpu3.memDep0.conflictingStores 35338 # Number of conflicting stores.
system.cpu3.iq.iqInstsAdded 246413 # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqNonSpecInstsAdded 6255 # Number of non-speculative instructions added to the IQ
system.cpu3.iq.iqInstsIssued 248738 # Number of instructions issued
system.cpu3.iq.iqSquashedInstsIssued 58 # Number of squashed instructions issued
system.cpu3.iq.iqSquashedInstsExamined 10413 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu3.iq.iqSquashedOperandsExamined 9948 # Number of squashed operands that are examined and possibly removed from graph
system.cpu3.iq.iqSquashedNonSpecRemoved 566 # Number of squashed non-spec instructions that were removed
system.cpu3.iq.issued_per_cycle::samples 175543 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::mean 1.416963 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::stdev 1.309147 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::0 66501 37.88% 37.88% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::1 22275 12.69% 50.57% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::2 40683 23.18% 73.75% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::3 41300 23.53% 97.27% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::4 3253 1.85% 99.13% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::5 1166 0.66% 99.79% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::6 259 0.15% 99.94% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::7 47 0.03% 99.97% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::total 175543 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntAlu 17 6.44% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.44% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemRead 37 14.02% 20.45% # attempts to use FU when none available
system.cpu3.iq.fu_full::MemWrite 210 79.55% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IntAlu 119912 48.21% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.21% # Type of FU issued
system.cpu3.iq.FU_type_0::MemRead 89101 35.82% 84.03% # Type of FU issued
system.cpu3.iq.FU_type_0::MemWrite 39725 15.97% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::total 248738 # Type of FU issued
system.cpu3.iq.rate 1.405855 # Inst issue rate
system.cpu3.iq.fu_busy_cnt 264 # FU busy when requested
system.cpu3.iq.fu_busy_rate 0.001061 # FU busy rate (busy events/executed inst)
system.cpu3.iq.int_inst_queue_reads 673341 # Number of integer instruction queue reads
system.cpu3.iq.int_inst_queue_writes 263119 # Number of integer instruction queue writes
system.cpu3.iq.int_inst_queue_wakeup_accesses 246940 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
system.cpu3.iq.int_alu_accesses 249002 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
system.cpu3.iew.lsq.thread0.forwLoads 35155 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu3.iew.lsq.thread0.squashedLoads 2247 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu3.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations
system.cpu3.iew.lsq.thread0.squashedStores 1385 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu3.iew.iewSquashCycles 2300 # Number of cycles IEW is squashing
system.cpu3.iew.iewBlockCycles 643 # Number of cycles IEW is blocking
system.cpu3.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking
system.cpu3.iew.iewDispatchedInsts 294126 # Number of instructions dispatched to IQ
system.cpu3.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch
system.cpu3.iew.iewDispLoadInsts 84722 # Number of dispatched load instructions
system.cpu3.iew.iewDispStoreInsts 40383 # Number of dispatched store instructions
system.cpu3.iew.iewDispNonSpecInsts 1060 # Number of dispatched non-speculative instructions
system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu3.iew.memOrderViolationEvents 38 # Number of memory order violations
system.cpu3.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly
system.cpu3.iew.predictedNotTakenIncorrect 919 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.branchMispredicts 1378 # Number of branch mispredicts detected at execute
system.cpu3.iew.iewExecutedInsts 247584 # Number of executed instructions
system.cpu3.iew.iewExecLoadInsts 83851 # Number of load instructions executed
system.cpu3.iew.iewExecSquashedInsts 1154 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
system.cpu3.iew.exec_nop 41458 # number of nop insts executed
system.cpu3.iew.exec_refs 123507 # number of memory reference insts executed
system.cpu3.iew.exec_branches 50799 # Number of branches executed
system.cpu3.iew.exec_stores 39656 # Number of stores executed
system.cpu3.iew.exec_rate 1.399333 # Inst execution rate
system.cpu3.iew.wb_sent 247229 # cumulative count of insts sent to commit
system.cpu3.iew.wb_count 246940 # cumulative count of insts written-back
system.cpu3.iew.wb_producers 140247 # num instructions producing a value
system.cpu3.iew.wb_consumers 144914 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu3.iew.wb_rate 1.395693 # insts written-back per cycle
system.cpu3.iew.wb_fanout 0.967795 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitSquashedInsts 11951 # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls 5689 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts 1265 # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::samples 165494 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::mean 1.704926 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::stdev 2.039126 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::0 64312 38.86% 38.86% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::1 48901 29.55% 68.41% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::2 6087 3.68% 72.09% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::3 6636 4.01% 76.10% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::4 1574 0.95% 77.05% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::5 35663 21.55% 98.60% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::6 504 0.30% 98.90% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::7 999 0.60% 99.51% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::8 818 0.49% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total 165494 # Number of insts commited each cycle
system.cpu3.commit.committedInsts 282155 # Number of instructions committed
system.cpu3.commit.committedOps 282155 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu3.commit.refs 121473 # Number of memory references committed
system.cpu3.commit.loads 82475 # Number of loads committed
system.cpu3.commit.membars 4979 # Number of memory barriers committed
system.cpu3.commit.branches 49942 # Number of branches committed
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu3.commit.int_insts 193540 # Number of committed integer instructions.
system.cpu3.commit.function_calls 322 # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass 40736 14.44% 14.44% # Class of committed instruction
system.cpu3.commit.op_class_0::IntAlu 114967 40.75% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.18% # Class of committed instruction
system.cpu3.commit.op_class_0::MemRead 87454 31.00% 86.18% # Class of committed instruction
system.cpu3.commit.op_class_0::MemWrite 38998 13.82% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total 282155 # Class of committed instruction
system.cpu3.commit.bw_lim_events 818 # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu3.rob.rob_reads 458195 # The number of ROB reads
system.cpu3.rob.rob_writes 590518 # The number of ROB writes
system.cpu3.timesIdled 210 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.idleCycles 1387 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 44814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts 236440 # Number of Instructions Simulated
system.cpu3.committedOps 236440 # Number of Ops (including micro ops) Simulated
system.cpu3.committedInsts_total 236440 # Number of Instructions Simulated
system.cpu3.cpi 0.748308 # CPI: Cycles Per Instruction
system.cpu3.cpi_total 0.748308 # CPI: Total CPI of All Threads
system.cpu3.ipc 1.336348 # IPC: Instructions Per Cycle
system.cpu3.ipc_total 1.336348 # IPC: Total IPC of All Threads
system.cpu3.int_regfile_reads 429141 # number of integer regfile reads
system.cpu3.int_regfile_writes 199912 # number of integer regfile writes
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
system.cpu3.misc_regfile_reads 125101 # number of misc regfile reads
system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
system.cpu3.icache.tags.replacements 319 # number of replacements
system.cpu3.icache.tags.tagsinuse 80.524551 # Cycle average of tags in use
system.cpu3.icache.tags.total_refs 19102 # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs 430 # Sample count of references to valid blocks.
system.cpu3.icache.tags.avg_refs 44.423256 # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.524551 # Average occupied blocks per requestor
system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157275 # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_percent::total 0.157275 # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id
system.cpu3.icache.tags.tag_accesses 20007 # Number of tag accesses
system.cpu3.icache.tags.data_accesses 20007 # Number of data accesses
system.cpu3.icache.ReadReq_hits::cpu3.inst 19102 # number of ReadReq hits
system.cpu3.icache.ReadReq_hits::total 19102 # number of ReadReq hits
system.cpu3.icache.demand_hits::cpu3.inst 19102 # number of demand (read+write) hits
system.cpu3.icache.demand_hits::total 19102 # number of demand (read+write) hits
system.cpu3.icache.overall_hits::cpu3.inst 19102 # number of overall hits
system.cpu3.icache.overall_hits::total 19102 # number of overall hits
system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses
system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses
system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses
system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses
system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses
system.cpu3.icache.overall_misses::total 475 # number of overall misses
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6525745 # number of ReadReq miss cycles
system.cpu3.icache.ReadReq_miss_latency::total 6525745 # number of ReadReq miss cycles
system.cpu3.icache.demand_miss_latency::cpu3.inst 6525745 # number of demand (read+write) miss cycles
system.cpu3.icache.demand_miss_latency::total 6525745 # number of demand (read+write) miss cycles
system.cpu3.icache.overall_miss_latency::cpu3.inst 6525745 # number of overall miss cycles
system.cpu3.icache.overall_miss_latency::total 6525745 # number of overall miss cycles
system.cpu3.icache.ReadReq_accesses::cpu3.inst 19577 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_accesses::total 19577 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.demand_accesses::cpu3.inst 19577 # number of demand (read+write) accesses
system.cpu3.icache.demand_accesses::total 19577 # number of demand (read+write) accesses
system.cpu3.icache.overall_accesses::cpu3.inst 19577 # number of overall (read+write) accesses
system.cpu3.icache.overall_accesses::total 19577 # number of overall (read+write) accesses
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.024263 # miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_miss_rate::total 0.024263 # miss rate for ReadReq accesses
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024263 # miss rate for demand accesses
system.cpu3.icache.demand_miss_rate::total 0.024263 # miss rate for demand accesses
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024263 # miss rate for overall accesses
system.cpu3.icache.overall_miss_rate::total 0.024263 # miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13738.410526 # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_miss_latency::total 13738.410526 # average ReadReq miss latency
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13738.410526 # average overall miss latency
system.cpu3.icache.demand_avg_miss_latency::total 13738.410526 # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13738.410526 # average overall miss latency
system.cpu3.icache.overall_avg_miss_latency::total 13738.410526 # average overall miss latency
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 45 # number of ReadReq MSHR hits
system.cpu3.icache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits
system.cpu3.icache.demand_mshr_hits::cpu3.inst 45 # number of demand (read+write) MSHR hits
system.cpu3.icache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits
system.cpu3.icache.overall_mshr_hits::cpu3.inst 45 # number of overall MSHR hits
system.cpu3.icache.overall_mshr_hits::total 45 # number of overall MSHR hits
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 430 # number of ReadReq MSHR misses
system.cpu3.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
system.cpu3.icache.demand_mshr_misses::cpu3.inst 430 # number of demand (read+write) MSHR misses
system.cpu3.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses
system.cpu3.icache.overall_mshr_misses::cpu3.inst 430 # number of overall MSHR misses
system.cpu3.icache.overall_mshr_misses::total 430 # number of overall MSHR misses
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5298255 # number of ReadReq MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_latency::total 5298255 # number of ReadReq MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5298255 # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.demand_mshr_miss_latency::total 5298255 # number of demand (read+write) MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5298255 # number of overall MSHR miss cycles
system.cpu3.icache.overall_mshr_miss_latency::total 5298255 # number of overall MSHR miss cycles
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021965 # mshr miss rate for ReadReq accesses
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for demand accesses
system.cpu3.icache.demand_mshr_miss_rate::total 0.021965 # mshr miss rate for demand accesses
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021965 # mshr miss rate for overall accesses
system.cpu3.icache.overall_mshr_miss_rate::total 0.021965 # mshr miss rate for overall accesses
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average ReadReq mshr miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12321.523256 # average ReadReq mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average overall mshr miss latency
system.cpu3.icache.demand_avg_mshr_miss_latency::total 12321.523256 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12321.523256 # average overall mshr miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency::total 12321.523256 # average overall mshr miss latency
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.tags.replacements 0 # number of replacements
system.cpu3.dcache.tags.tagsinuse 24.706550 # Cycle average of tags in use
system.cpu3.dcache.tags.total_refs 44992 # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
system.cpu3.dcache.tags.avg_refs 1606.857143 # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.706550 # Average occupied blocks per requestor
system.cpu3.dcache.tags.occ_percent::cpu3.data 0.048255 # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_percent::total 0.048255 # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
system.cpu3.dcache.tags.tag_accesses 350946 # Number of tag accesses
system.cpu3.dcache.tags.data_accesses 350946 # Number of data accesses
system.cpu3.dcache.ReadReq_hits::cpu3.data 48327 # number of ReadReq hits
system.cpu3.dcache.ReadReq_hits::total 48327 # number of ReadReq hits
system.cpu3.dcache.WriteReq_hits::cpu3.data 38795 # number of WriteReq hits
system.cpu3.dcache.WriteReq_hits::total 38795 # number of WriteReq hits
system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits
system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
system.cpu3.dcache.demand_hits::cpu3.data 87122 # number of demand (read+write) hits
system.cpu3.dcache.demand_hits::total 87122 # number of demand (read+write) hits
system.cpu3.dcache.overall_hits::cpu3.data 87122 # number of overall hits
system.cpu3.dcache.overall_hits::total 87122 # number of overall hits
system.cpu3.dcache.ReadReq_misses::cpu3.data 351 # number of ReadReq misses
system.cpu3.dcache.ReadReq_misses::total 351 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 139 # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total 139 # number of WriteReq misses
system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses
system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses
system.cpu3.dcache.demand_misses::cpu3.data 490 # number of demand (read+write) misses
system.cpu3.dcache.demand_misses::total 490 # number of demand (read+write) misses
system.cpu3.dcache.overall_misses::cpu3.data 490 # number of overall misses
system.cpu3.dcache.overall_misses::total 490 # number of overall misses
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 4621144 # number of ReadReq miss cycles
system.cpu3.dcache.ReadReq_miss_latency::total 4621144 # number of ReadReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3311512 # number of WriteReq miss cycles
system.cpu3.dcache.WriteReq_miss_latency::total 3311512 # number of WriteReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 513008 # number of SwapReq miss cycles
system.cpu3.dcache.SwapReq_miss_latency::total 513008 # number of SwapReq miss cycles
system.cpu3.dcache.demand_miss_latency::cpu3.data 7932656 # number of demand (read+write) miss cycles
system.cpu3.dcache.demand_miss_latency::total 7932656 # number of demand (read+write) miss cycles
system.cpu3.dcache.overall_miss_latency::cpu3.data 7932656 # number of overall miss cycles
system.cpu3.dcache.overall_miss_latency::total 7932656 # number of overall miss cycles
system.cpu3.dcache.ReadReq_accesses::cpu3.data 48678 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_accesses::total 48678 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::cpu3.data 38934 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.WriteReq_accesses::total 38934 # number of WriteReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::cpu3.data 64 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.SwapReq_accesses::total 64 # number of SwapReq accesses(hits+misses)
system.cpu3.dcache.demand_accesses::cpu3.data 87612 # number of demand (read+write) accesses
system.cpu3.dcache.demand_accesses::total 87612 # number of demand (read+write) accesses
system.cpu3.dcache.overall_accesses::cpu3.data 87612 # number of overall (read+write) accesses
system.cpu3.dcache.overall_accesses::total 87612 # number of overall (read+write) accesses
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.007211 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_miss_rate::total 0.007211 # miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003570 # miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_miss_rate::total 0.003570 # miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.812500 # miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_miss_rate::total 0.812500 # miss rate for SwapReq accesses
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005593 # miss rate for demand accesses
system.cpu3.dcache.demand_miss_rate::total 0.005593 # miss rate for demand accesses
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005593 # miss rate for overall accesses
system.cpu3.dcache.overall_miss_rate::total 0.005593 # miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13165.652422 # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_miss_latency::total 13165.652422 # average ReadReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23823.827338 # average WriteReq miss latency
system.cpu3.dcache.WriteReq_avg_miss_latency::total 23823.827338 # average WriteReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9865.538462 # average SwapReq miss latency
system.cpu3.dcache.SwapReq_avg_miss_latency::total 9865.538462 # average SwapReq miss latency
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16189.093878 # average overall miss latency
system.cpu3.dcache.demand_avg_miss_latency::total 16189.093878 # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16189.093878 # average overall miss latency
system.cpu3.dcache.overall_avg_miss_latency::total 16189.093878 # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 197 # number of ReadReq MSHR hits
system.cpu3.dcache.ReadReq_mshr_hits::total 197 # number of ReadReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 33 # number of WriteReq MSHR hits
system.cpu3.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits
system.cpu3.dcache.demand_mshr_hits::cpu3.data 230 # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_hits::total 230 # number of demand (read+write) MSHR hits
system.cpu3.dcache.overall_mshr_hits::cpu3.data 230 # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_hits::total 230 # number of overall MSHR hits
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 154 # number of ReadReq MSHR misses
system.cpu3.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses
system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses
system.cpu3.dcache.demand_mshr_misses::cpu3.data 260 # number of demand (read+write) MSHR misses
system.cpu3.dcache.demand_mshr_misses::total 260 # number of demand (read+write) MSHR misses
system.cpu3.dcache.overall_mshr_misses::cpu3.data 260 # number of overall MSHR misses
system.cpu3.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1052517 # number of ReadReq MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1052517 # number of ReadReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1403488 # number of WriteReq MSHR miss cycles
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1403488 # number of WriteReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 408992 # number of SwapReq MSHR miss cycles
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 408992 # number of SwapReq MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2456005 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_latency::total 2456005 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2456005 # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_latency::total 2456005 # number of overall MSHR miss cycles
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003164 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003164 # mshr miss rate for ReadReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002723 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002723 # mshr miss rate for WriteReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.812500 # mshr miss rate for SwapReq accesses
system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.812500 # mshr miss rate for SwapReq accesses
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002968 # mshr miss rate for demand accesses
system.cpu3.dcache.demand_mshr_miss_rate::total 0.002968 # mshr miss rate for demand accesses
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002968 # mshr miss rate for overall accesses
system.cpu3.dcache.overall_mshr_miss_rate::total 0.002968 # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6834.525974 # average ReadReq mshr miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6834.525974 # average ReadReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13240.452830 # average WriteReq mshr miss latency
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13240.452830 # average WriteReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7865.230769 # average SwapReq mshr miss latency
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7865.230769 # average SwapReq mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9446.173077 # average overall mshr miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9446.173077 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9446.173077 # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9446.173077 # average overall mshr miss latency
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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