gem5/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
Andreas Hansson b63631536d stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.

The main reason for bundling them up is to minimise the changeset
size.
2013-08-19 03:52:36 -04:00

407 lines
46 KiB
Text

---------- Begin Simulation Statistics ----------
sim_seconds 0.000032 # Number of seconds simulated
sim_ticks 31633000 # Number of ticks simulated
final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 304637 # Simulator instruction rate (inst/s)
host_op_rate 304230 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1653175117 # Simulator tick rate (ticks/s)
host_mem_usage 224940 # Number of bytes of host memory used
host_seconds 0.02 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
system.physmem.bytes_read::total 28096 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 439 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 608984289 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 279202099 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 888186388 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 608984289 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 608984289 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 888186388 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 388 # Transaction distribution
system.membus.trans_dist::ReadResp 388 # Transaction distribution
system.membus.trans_dist::ReadExReq 51 # Transaction distribution
system.membus.trans_dist::ReadExResp 51 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 878 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28096 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 28096 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
system.membus.respLayer1.occupancy 3951000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 12.5 # Layer utilization (%)
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
system.cpu.numCycles 63266 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 5814 # Number of instructions committed
system.cpu.committedOps 5814 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_func_calls 194 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls
system.cpu.num_int_insts 5113 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
system.cpu.num_int_register_reads 7284 # number of times the integer registers were read
system.cpu.num_int_register_writes 3397 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
system.cpu.num_mem_refs 2089 # number of memory refs
system.cpu.num_load_insts 1163 # Number of load instructions
system.cpu.num_store_insts 926 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 63266 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.tags.replacements 13 # number of replacements
system.cpu.icache.tags.tagsinuse 132.545353 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 5513 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 303 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 18.194719 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 132.545353 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.064719 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.064719 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 5513 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 5513 # number of overall hits
system.cpu.icache.overall_hits::total 5513 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 303 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 303 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses
system.cpu.icache.overall_misses::total 303 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 16581000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 16581000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 16581000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 16581000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 16581000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 16581000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 5816 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 5816 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 5816 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 5816 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 5816 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 5816 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052098 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.052098 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.052098 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.052098 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.052098 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.052098 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54722.772277 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54722.772277 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54722.772277 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54722.772277 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54722.772277 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 303 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 303 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15975000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 15975000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15975000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 15975000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052098 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.052098 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.052098 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 188.114191 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 388 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.005155 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 133.890657 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 54.223533 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004086 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001655 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 388 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 439 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.l2cache.overall_misses::total 439 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15652000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4524000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 20176000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2652000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 2652000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 15652000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22828000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 15652000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22828000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 303 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 390 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 303 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 303 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.994872 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.995465 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.995465 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 388 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 439 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12040000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15520000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2040000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2040000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12040000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 17560000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12040000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994872 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995465 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995465 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 87.492114 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1950 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 14.130435 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.021360 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1950 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1950 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1950 # number of overall hits
system.cpu.dcache.overall_hits::total 1950 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 51 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 51 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
system.cpu.dcache.overall_misses::total 138 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2805000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2805000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074807 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.074807 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.055135 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.066092 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.066092 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.066092 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.066092 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 892232795 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 390 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 606 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19392 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 28224 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 454500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
---------- End Simulation Statistics ----------