gem5/tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
Steve Reinhardt 7b40c36fbd Update stats for new single bad-address responder.
Mostly just config.ini updates, though the different response
latency for bad addresses caused very minor timing changes
in the O3 Linux boot tests.
2009-04-22 01:55:52 -04:00

19 lines
1.7 KiB
Text

---------- Begin Simulation Statistics ----------
host_inst_rate 2338829 # Simulator instruction rate (inst/s)
host_mem_usage 501616 # Number of bytes of host memory used
host_seconds 953.11 # Real time elapsed on the host
host_tick_rate 2343672 # Simulator tick rate (ticks/s)
sim_freq 2000000000 # Frequency of simulated ticks
sim_insts 2229160714 # Number of instructions simulated
sim_seconds 1.116889 # Number of seconds simulated
sim_ticks 2233777512 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 2233777513 # number of cpu cycles simulated
system.cpu.num_insts 2229160714 # Number of instructions executed
system.cpu.num_refs 547951940 # Number of memory references
---------- End Simulation Statistics ----------