36581a5342
cpu/checker/cpu.cc:
Fixups for fetch fault being sent with the instruction.
cpu/o3/fetch_impl.hh:
cpu/ozone/front_end_impl.hh:
Send any faults generated at fetch along with a fake nop instruction to the back end. This avoids having to use direct communication to check if the entire front end has drained; it is naturally handled through the nop's fault being handled when it reaches the head of commit.
cpu/ozone/front_end.hh:
Add extra status TrapPending.
cpu/ozone/lw_back_end_impl.hh:
Fetch fault handled through a dummy nop carrying the fetch fault.
Avoid putting Nops on the exeList.
--HG--
extra : convert_revision : 8d9899748b34c204763a49c48a9b5113864f5789
926 lines
24 KiB
C++
926 lines
24 KiB
C++
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#include "arch/faults.hh"
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#include "arch/isa_traits.hh"
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#include "base/statistics.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/ozone/front_end.hh"
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#include "mem/mem_interface.hh"
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#include "sim/byte_swap.hh"
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using namespace TheISA;
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template <class Impl>
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FrontEnd<Impl>::FrontEnd(Params *params)
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: branchPred(params),
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icacheInterface(params->icacheInterface),
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instBufferSize(0),
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maxInstBufferSize(params->maxInstBufferSize),
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width(params->frontEndWidth),
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freeRegs(params->numPhysicalRegs),
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numPhysRegs(params->numPhysicalRegs),
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serializeNext(false),
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interruptPending(false)
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{
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switchedOut = false;
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status = Idle;
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// Setup branch predictor.
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// Setup Memory Request
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/*
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memReq = new MemReq();
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memReq->asid = 0;
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memReq->data = new uint8_t[64];
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*/
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memReq = NULL;
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// Size of cache block.
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cacheBlkSize = icacheInterface ? icacheInterface->getBlockSize() : 64;
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assert(isPowerOf2(cacheBlkSize));
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// Create mask to get rid of offset bits.
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cacheBlkMask = (cacheBlkSize - 1);
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// Create space to store a cache line.
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cacheData = new uint8_t[cacheBlkSize];
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fetchCacheLineNextCycle = true;
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cacheBlkValid = false;
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#if !FULL_SYSTEM
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// pTable = params->pTable;
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#endif
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fetchFault = NoFault;
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}
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template <class Impl>
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std::string
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FrontEnd<Impl>::name() const
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{
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return cpu->name() + ".frontend";
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}
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template <class Impl>
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void
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FrontEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
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{
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comm = _comm;
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// @todo: Hardcoded for now. Allow this to be set by a latency.
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fromCommit = comm->getWire(-1);
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}
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template <class Impl>
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void
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FrontEnd<Impl>::setXC(ExecContext *xc_ptr)
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{
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xc = xc_ptr;
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// memReq->xc = xc;
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}
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template <class Impl>
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void
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FrontEnd<Impl>::regStats()
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{
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icacheStallCycles
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.name(name() + ".icacheStallCycles")
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.desc("Number of cycles fetch is stalled on an Icache miss")
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.prereq(icacheStallCycles);
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fetchedInsts
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.name(name() + ".fetchedInsts")
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.desc("Number of instructions fetch has processed")
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.prereq(fetchedInsts);
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fetchedBranches
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.name(name() + ".fetchedBranches")
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.desc("Number of fetched branches")
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.prereq(fetchedBranches);
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predictedBranches
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.name(name() + ".predictedBranches")
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.desc("Number of branches that fetch has predicted taken")
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.prereq(predictedBranches);
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fetchCycles
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.name(name() + ".fetchCycles")
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.desc("Number of cycles fetch has run and was not squashing or"
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" blocked")
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.prereq(fetchCycles);
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fetchIdleCycles
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.name(name() + ".fetchIdleCycles")
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.desc("Number of cycles fetch was idle")
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.prereq(fetchIdleCycles);
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fetchSquashCycles
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.name(name() + ".fetchSquashCycles")
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.desc("Number of cycles fetch has spent squashing")
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.prereq(fetchSquashCycles);
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fetchBlockedCycles
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.name(name() + ".fetchBlockedCycles")
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.desc("Number of cycles fetch has spent blocked")
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.prereq(fetchBlockedCycles);
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fetchedCacheLines
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.name(name() + ".fetchedCacheLines")
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.desc("Number of cache lines fetched")
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.prereq(fetchedCacheLines);
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fetchIcacheSquashes
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.name(name() + ".fetchIcacheSquashes")
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.desc("Number of outstanding Icache misses that were squashed")
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.prereq(fetchIcacheSquashes);
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fetchNisnDist
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.init(/* base value */ 0,
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/* last value */ width,
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/* bucket size */ 1)
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.name(name() + ".rateDist")
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.desc("Number of instructions fetched each cycle (Total)")
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.flags(Stats::pdf);
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idleRate
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.name(name() + ".idleRate")
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.desc("Percent of cycles fetch was idle")
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.prereq(idleRate);
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idleRate = fetchIdleCycles * 100 / cpu->numCycles;
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branchRate
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.name(name() + ".branchRate")
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.desc("Number of branch fetches per cycle")
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.flags(Stats::total);
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branchRate = fetchedBranches / cpu->numCycles;
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fetchRate
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.name(name() + ".rate")
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.desc("Number of inst fetches per cycle")
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.flags(Stats::total);
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fetchRate = fetchedInsts / cpu->numCycles;
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IFQCount
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.name(name() + ".IFQ:count")
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.desc("cumulative IFQ occupancy")
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;
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IFQFcount
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.name(name() + ".IFQ:fullCount")
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.desc("cumulative IFQ full count")
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.flags(Stats::total)
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;
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IFQOccupancy
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.name(name() + ".IFQ:occupancy")
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.desc("avg IFQ occupancy (inst's)")
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;
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IFQOccupancy = IFQCount / cpu->numCycles;
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IFQLatency
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.name(name() + ".IFQ:latency")
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.desc("avg IFQ occupant latency (cycle's)")
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.flags(Stats::total)
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;
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IFQFullRate
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.name(name() + ".IFQ:fullRate")
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.desc("fraction of time (cycles) IFQ was full")
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.flags(Stats::total);
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;
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IFQFullRate = IFQFcount * Stats::constant(100) / cpu->numCycles;
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dispatchCountStat
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.name(name() + ".DIS:count")
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.desc("cumulative count of dispatched insts")
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.flags(Stats::total)
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;
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dispatchedSerializing
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.name(name() + ".DIS:serializingInsts")
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.desc("count of serializing insts dispatched")
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.flags(Stats::total)
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;
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dispatchedTempSerializing
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.name(name() + ".DIS:tempSerializingInsts")
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.desc("count of temporary serializing insts dispatched")
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.flags(Stats::total)
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;
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dispatchSerializeStallCycles
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.name(name() + ".DIS:serializeStallCycles")
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.desc("count of cycles dispatch stalled for serializing inst")
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.flags(Stats::total)
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;
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dispatchRate
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.name(name() + ".DIS:rate")
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.desc("dispatched insts per cycle")
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.flags(Stats::total)
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;
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dispatchRate = dispatchCountStat / cpu->numCycles;
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regIntFull
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.name(name() + ".REG:int:full")
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.desc("number of cycles where there were no INT registers")
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;
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regFpFull
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.name(name() + ".REG:fp:full")
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.desc("number of cycles where there were no FP registers")
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;
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IFQLatency = IFQOccupancy / dispatchRate;
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branchPred.regStats();
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}
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template <class Impl>
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void
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FrontEnd<Impl>::tick()
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{
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if (switchedOut)
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return;
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// @todo: Maybe I want to just have direct communication...
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if (fromCommit->doneSeqNum) {
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branchPred.update(fromCommit->doneSeqNum, 0);
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}
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IFQCount += instBufferSize;
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IFQFcount += instBufferSize == maxInstBufferSize;
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// Fetch cache line
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if (status == IcacheMissComplete) {
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cacheBlkValid = true;
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status = Running;
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if (barrierInst)
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status = SerializeBlocked;
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if (freeRegs <= 0)
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status = RenameBlocked;
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checkBE();
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} else if (status == IcacheMissStall) {
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DPRINTF(FE, "Still in Icache miss stall.\n");
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icacheStallCycles++;
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return;
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}
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if (status == RenameBlocked || status == SerializeBlocked ||
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status == TrapPending || status == BEBlocked) {
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// Will cause a one cycle bubble between changing state and
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// restarting.
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DPRINTF(FE, "In blocked status.\n");
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fetchBlockedCycles++;
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if (status == SerializeBlocked) {
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dispatchSerializeStallCycles++;
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}
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updateStatus();
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return;
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} else if (status == QuiescePending) {
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DPRINTF(FE, "Waiting for quiesce to execute or get squashed.\n");
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return;
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} else if (status != IcacheMissComplete) {
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if (fetchCacheLineNextCycle) {
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Fault fault = fetchCacheLine();
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if (fault != NoFault) {
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handleFault(fault);
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fetchFault = fault;
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return;
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}
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fetchCacheLineNextCycle = false;
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}
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// If miss, stall until it returns.
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if (status == IcacheMissStall) {
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// Tell CPU to not tick me for now.
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return;
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}
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}
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fetchCycles++;
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int num_inst = 0;
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// Otherwise loop and process instructions.
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// One way to hack infinite width is to set width and maxInstBufferSize
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// both really high. Inelegant, but probably will work.
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while (num_inst < width &&
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instBufferSize < maxInstBufferSize) {
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// Get instruction from cache line.
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DynInstPtr inst = getInstFromCacheline();
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if (!inst) {
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// PC is no longer in the cache line, end fetch.
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// Might want to check this at the end of the cycle so that
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// there's no cycle lost to checking for a new cache line.
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DPRINTF(FE, "Need to get new cache line\n");
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fetchCacheLineNextCycle = true;
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break;
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}
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// if (generalizeFetch) {
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processInst(inst);
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if (status == SerializeBlocked) {
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break;
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}
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// Possibly push into a time buffer that estimates the front end
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// latency
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instBuffer.push_back(inst);
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++instBufferSize;
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++num_inst;
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// } else {
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// fetch(num_inst);
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// decode(num_inst);
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// rename(num_inst);
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// }
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#if FULL_SYSTEM
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if (inst->isQuiesce()) {
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warn("%lli: Quiesce instruction encountered, halting fetch!", curTick);
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status = QuiescePending;
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break;
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}
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#endif
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if (inst->predTaken()) {
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// Start over with tick?
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break;
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} else if (freeRegs <= 0) {
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DPRINTF(FE, "Ran out of free registers to rename to!\n");
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status = RenameBlocked;
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break;
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} else if (serializeNext) {
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break;
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}
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}
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fetchNisnDist.sample(num_inst);
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checkBE();
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DPRINTF(FE, "Num insts processed: %i, Inst Buffer size: %i, Free "
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"Regs %i\n", num_inst, instBufferSize, freeRegs);
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}
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template <class Impl>
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Fault
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FrontEnd<Impl>::fetchCacheLine()
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{
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// Read a cache line, based on the current PC.
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#if FULL_SYSTEM
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// Flag to say whether or not address is physical addr.
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unsigned flags = cpu->inPalMode(PC) ? PHYSICAL : 0;
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#else
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unsigned flags = 0;
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#endif // FULL_SYSTEM
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Fault fault = NoFault;
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if (interruptPending && flags == 0) {
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return fault;
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}
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// Align the fetch PC so it's at the start of a cache block.
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Addr fetch_PC = icacheBlockAlignPC(PC);
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DPRINTF(FE, "Fetching cache line starting at %#x.\n", fetch_PC);
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// Setup the memReq to do a read of the first isntruction's address.
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// Set the appropriate read size and flags as well.
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memReq = new MemReq();
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memReq->asid = 0;
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memReq->thread_num = 0;
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memReq->data = new uint8_t[64];
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memReq->xc = xc;
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memReq->cmd = Read;
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memReq->reset(fetch_PC, cacheBlkSize, flags);
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// Translate the instruction request.
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fault = cpu->translateInstReq(memReq);
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// In the case of faults, the fetch stage may need to stall and wait
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// on what caused the fetch (ITB or Icache miss).
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// assert(fault == NoFault);
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// Now do the timing access to see whether or not the instruction
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// exists within the cache.
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if (icacheInterface && fault == NoFault) {
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#if FULL_SYSTEM
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if (cpu->system->memctrl->badaddr(memReq->paddr) ||
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memReq->flags & UNCACHEABLE) {
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DPRINTF(FE, "Fetch: Bad address %#x (hopefully on a "
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"misspeculating path!",
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memReq->paddr);
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return TheISA::genMachineCheckFault();
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}
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#endif
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memReq->completionEvent = NULL;
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memReq->time = curTick;
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fault = cpu->mem->read(memReq, cacheData);
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MemAccessResult res = icacheInterface->access(memReq);
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// If the cache missed then schedule an event to wake
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// up this stage once the cache miss completes.
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if (icacheInterface->doEvents() && res != MA_HIT) {
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memReq->completionEvent = new ICacheCompletionEvent(memReq, this);
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status = IcacheMissStall;
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cacheBlkValid = false;
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DPRINTF(FE, "Cache miss.\n");
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} else {
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DPRINTF(FE, "Cache hit.\n");
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cacheBlkValid = true;
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// memcpy(cacheData, memReq->data, memReq->size);
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}
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}
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// Note that this will set the cache block PC a bit earlier than it should
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// be set.
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cacheBlkPC = fetch_PC;
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++fetchedCacheLines;
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DPRINTF(FE, "Done fetching cache line.\n");
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return fault;
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}
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template <class Impl>
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void
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FrontEnd<Impl>::processInst(DynInstPtr &inst)
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{
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if (processBarriers(inst)) {
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return;
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}
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Addr inst_PC = inst->readPC();
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// BPredInfo bp_info = branchPred.lookup(inst_PC);
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if (!inst->isControl()) {
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inst->setPredTarg(inst->readNextPC());
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} else {
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fetchedBranches++;
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if (branchPred.predict(inst, inst_PC, inst->threadNumber)) {
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predictedBranches++;
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}
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}
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Addr next_PC = inst->readPredTarg();
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DPRINTF(FE, "[sn:%lli] Predicted and processed inst PC %#x, next PC "
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"%#x\n", inst->seqNum, inst_PC, next_PC);
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// inst->setNextPC(next_PC);
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// inst->setBPredInfo(bp_info);
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// Not sure where I should set this
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PC = next_PC;
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renameInst(inst);
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}
|
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|
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template <class Impl>
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bool
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FrontEnd<Impl>::processBarriers(DynInstPtr &inst)
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{
|
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if (serializeNext) {
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inst->setSerializeBefore();
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serializeNext = false;
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} else if (!inst->isSerializing()) {
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return false;
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}
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if (inst->isSerializeBefore() && !inst->isSerializeHandled()) {
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DPRINTF(FE, "Serialize before instruction encountered.\n");
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|
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if (!inst->isTempSerializeBefore()) {
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dispatchedSerializing++;
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inst->setSerializeHandled();
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} else {
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dispatchedTempSerializing++;
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}
|
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|
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// Change status over to SerializeBlocked so that other stages know
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// what this is blocked on.
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status = SerializeBlocked;
|
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barrierInst = inst;
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return true;
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} else if (inst->isSerializeAfter() && !inst->isSerializeHandled()) {
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DPRINTF(FE, "Serialize after instruction encountered.\n");
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inst->setSerializeHandled();
|
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|
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dispatchedSerializing++;
|
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serializeNext = true;
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return false;
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}
|
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return false;
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}
|
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|
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template <class Impl>
|
|
void
|
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FrontEnd<Impl>::handleFault(Fault &fault)
|
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{
|
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DPRINTF(FE, "Fault at fetch, telling commit\n");
|
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// backEnd->fetchFault(fault);
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// We're blocked on the back end until it handles this fault.
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status = TrapPending;
|
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|
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// Get a sequence number.
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InstSeqNum inst_seq = getAndIncrementInstSeq();
|
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// We will use a nop in order to carry the fault.
|
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ExtMachInst ext_inst = TheISA::NoopMachInst;
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|
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// Create a new DynInst from the dummy nop.
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DynInstPtr instruction = new DynInst(ext_inst, PC,
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PC+sizeof(MachInst),
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inst_seq, cpu);
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instruction->setPredTarg(instruction->readNextPC());
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// instruction->setThread(tid);
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|
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// instruction->setASID(tid);
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|
|
instruction->setState(thread);
|
|
|
|
instruction->traceData = NULL;
|
|
|
|
instruction->fault = fault;
|
|
instruction->setCanIssue();
|
|
instBuffer.push_back(instruction);
|
|
++instBufferSize;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
FrontEnd<Impl>::squash(const InstSeqNum &squash_num, const Addr &next_PC,
|
|
const bool is_branch, const bool branch_taken)
|
|
{
|
|
DPRINTF(FE, "Squashing from [sn:%lli], setting PC to %#x\n",
|
|
squash_num, next_PC);
|
|
|
|
if (fetchFault != NoFault)
|
|
fetchFault = NoFault;
|
|
|
|
while (!instBuffer.empty() &&
|
|
instBuffer.back()->seqNum > squash_num) {
|
|
DynInstPtr inst = instBuffer.back();
|
|
|
|
DPRINTF(FE, "Squashing instruction [sn:%lli] PC %#x\n",
|
|
inst->seqNum, inst->readPC());
|
|
|
|
inst->clearDependents();
|
|
|
|
instBuffer.pop_back();
|
|
--instBufferSize;
|
|
|
|
// Fix up branch predictor if necessary.
|
|
// branchPred.undo(inst->getBPredInfo());
|
|
|
|
freeRegs+= inst->numDestRegs();
|
|
}
|
|
|
|
// Copy over rename table from the back end.
|
|
renameTable.copyFrom(backEnd->renameTable);
|
|
|
|
PC = next_PC;
|
|
|
|
// Update BP with proper information.
|
|
if (is_branch) {
|
|
branchPred.squash(squash_num, next_PC, branch_taken, 0);
|
|
} else {
|
|
branchPred.squash(squash_num, 0);
|
|
}
|
|
|
|
// Clear the icache miss if it's outstanding.
|
|
if (status == IcacheMissStall && icacheInterface) {
|
|
DPRINTF(FE, "Squashing outstanding Icache miss.\n");
|
|
// icacheInterface->squash(0);
|
|
memReq = NULL;
|
|
}
|
|
|
|
if (status == SerializeBlocked) {
|
|
assert(barrierInst->seqNum > squash_num);
|
|
barrierInst = NULL;
|
|
}
|
|
|
|
// Unless this squash originated from the front end, we're probably
|
|
// in running mode now.
|
|
// Actually might want to make this latency dependent.
|
|
status = Running;
|
|
fetchCacheLineNextCycle = true;
|
|
}
|
|
|
|
template <class Impl>
|
|
typename Impl::DynInstPtr
|
|
FrontEnd<Impl>::getInst()
|
|
{
|
|
if (instBufferSize == 0) {
|
|
return NULL;
|
|
}
|
|
|
|
DynInstPtr inst = instBuffer.front();
|
|
|
|
instBuffer.pop_front();
|
|
|
|
--instBufferSize;
|
|
|
|
dispatchCountStat++;
|
|
|
|
return inst;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
FrontEnd<Impl>::processCacheCompletion(MemReqPtr &req)
|
|
{
|
|
DPRINTF(FE, "Processing cache completion\n");
|
|
|
|
// Do something here.
|
|
if (status != IcacheMissStall ||
|
|
req != memReq ||
|
|
switchedOut) {
|
|
DPRINTF(FE, "Previous fetch was squashed.\n");
|
|
fetchIcacheSquashes++;
|
|
return;
|
|
}
|
|
|
|
status = IcacheMissComplete;
|
|
|
|
/* if (checkStall(tid)) {
|
|
fetchStatus[tid] = Blocked;
|
|
} else {
|
|
fetchStatus[tid] = IcacheMissComplete;
|
|
}
|
|
*/
|
|
// memcpy(cacheData, memReq->data, memReq->size);
|
|
|
|
// Reset the completion event to NULL.
|
|
// memReq->completionEvent = NULL;
|
|
memReq = NULL;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
FrontEnd<Impl>::addFreeRegs(int num_freed)
|
|
{
|
|
if (status == RenameBlocked && freeRegs + num_freed > 0) {
|
|
status = Running;
|
|
}
|
|
|
|
DPRINTF(FE, "Adding %i freed registers\n", num_freed);
|
|
|
|
freeRegs+= num_freed;
|
|
|
|
// assert(freeRegs <= numPhysRegs);
|
|
if (freeRegs > numPhysRegs)
|
|
freeRegs = numPhysRegs;
|
|
}
|
|
|
|
template <class Impl>
|
|
bool
|
|
FrontEnd<Impl>::updateStatus()
|
|
{
|
|
// bool rename_block = freeRegs <= 0;
|
|
bool serialize_block = !backEnd->robEmpty() || instBufferSize;
|
|
bool be_block = cpu->decoupledFrontEnd ? false : backEnd->isBlocked();
|
|
bool ret_val = false;
|
|
/*
|
|
// Should already be handled through addFreeRegs function
|
|
if (status == RenameBlocked && !rename_block) {
|
|
status = Running;
|
|
ret_val = true;
|
|
}
|
|
*/
|
|
|
|
if (status == SerializeBlocked && !serialize_block) {
|
|
status = SerializeComplete;
|
|
ret_val = true;
|
|
}
|
|
|
|
if (status == BEBlocked && !be_block) {
|
|
if (barrierInst) {
|
|
status = SerializeBlocked;
|
|
} else {
|
|
status = Running;
|
|
}
|
|
ret_val = true;
|
|
}
|
|
return ret_val;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
FrontEnd<Impl>::checkBE()
|
|
{
|
|
bool be_block = cpu->decoupledFrontEnd ? false : backEnd->isBlocked();
|
|
if (be_block) {
|
|
if (status == Running || status == Idle) {
|
|
status = BEBlocked;
|
|
}
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
typename Impl::DynInstPtr
|
|
FrontEnd<Impl>::getInstFromCacheline()
|
|
{
|
|
if (status == SerializeComplete) {
|
|
DynInstPtr inst = barrierInst;
|
|
status = Running;
|
|
barrierInst = NULL;
|
|
inst->clearSerializeBefore();
|
|
return inst;
|
|
}
|
|
|
|
InstSeqNum inst_seq;
|
|
MachInst inst;
|
|
// @todo: Fix this magic number used here to handle word offset (and
|
|
// getting rid of PAL bit)
|
|
unsigned offset = (PC & cacheBlkMask) & ~3;
|
|
|
|
// PC of inst is not in this cache block
|
|
if (PC >= (cacheBlkPC + cacheBlkSize) || PC < cacheBlkPC || !cacheBlkValid) {
|
|
// DPRINTF(OoOCPU, "OoOCPU: PC is not in this cache block\n");
|
|
// DPRINTF(OoOCPU, "OoOCPU: PC: %#x, cacheBlkPC: %#x, cacheBlkValid: %i",
|
|
// PC, cacheBlkPC, cacheBlkValid);
|
|
// panic("Instruction not in cache line or cache line invalid!");
|
|
return NULL;
|
|
}
|
|
|
|
//////////////////////////
|
|
// Fetch one instruction
|
|
//////////////////////////
|
|
|
|
// Get a sequence number.
|
|
inst_seq = getAndIncrementInstSeq();
|
|
|
|
// Make sure this is a valid index.
|
|
assert(offset <= cacheBlkSize - sizeof(MachInst));
|
|
|
|
// Get the instruction from the array of the cache line.
|
|
inst = htog(*reinterpret_cast<MachInst *>(&cacheData[offset]));
|
|
|
|
ExtMachInst decode_inst = TheISA::makeExtMI(inst, PC);
|
|
|
|
// Create a new DynInst from the instruction fetched.
|
|
DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst),
|
|
inst_seq, cpu);
|
|
|
|
instruction->setState(thread);
|
|
|
|
DPRINTF(FE, "Instruction [sn:%lli] created, with PC %#x\n%s\n",
|
|
inst_seq, instruction->readPC(),
|
|
instruction->staticInst->disassemble(PC));
|
|
|
|
instruction->traceData =
|
|
Trace::getInstRecord(curTick, xc, cpu,
|
|
instruction->staticInst,
|
|
instruction->readPC(), 0);
|
|
|
|
// Increment stat of fetched instructions.
|
|
++fetchedInsts;
|
|
|
|
return instruction;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
FrontEnd<Impl>::renameInst(DynInstPtr &inst)
|
|
{
|
|
DynInstPtr src_inst = NULL;
|
|
int num_src_regs = inst->numSrcRegs();
|
|
if (num_src_regs == 0) {
|
|
inst->setCanIssue();
|
|
} else {
|
|
for (int i = 0; i < num_src_regs; ++i) {
|
|
src_inst = renameTable[inst->srcRegIdx(i)];
|
|
|
|
inst->setSrcInst(src_inst, i);
|
|
|
|
DPRINTF(FE, "[sn:%lli]: Src reg %i is inst [sn:%lli]\n",
|
|
inst->seqNum, (int)inst->srcRegIdx(i), src_inst->seqNum);
|
|
|
|
if (src_inst->isResultReady()) {
|
|
DPRINTF(FE, "Reg ready.\n");
|
|
inst->markSrcRegReady(i);
|
|
} else {
|
|
DPRINTF(FE, "Adding to dependent list.\n");
|
|
src_inst->addDependent(inst);
|
|
}
|
|
}
|
|
}
|
|
|
|
for (int i = 0; i < inst->numDestRegs(); ++i) {
|
|
RegIndex idx = inst->destRegIdx(i);
|
|
|
|
DPRINTF(FE, "Dest reg %i is now inst [sn:%lli], was previously "
|
|
"[sn:%lli]\n",
|
|
(int)inst->destRegIdx(i), inst->seqNum,
|
|
renameTable[idx]->seqNum);
|
|
|
|
inst->setPrevDestInst(renameTable[idx], i);
|
|
|
|
renameTable[idx] = inst;
|
|
--freeRegs;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
FrontEnd<Impl>::wakeFromQuiesce()
|
|
{
|
|
DPRINTF(FE, "Waking up from quiesce\n");
|
|
// Hopefully this is safe
|
|
status = Running;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
FrontEnd<Impl>::switchOut()
|
|
{
|
|
switchedOut = true;
|
|
cpu->signalSwitched();
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
FrontEnd<Impl>::doSwitchOut()
|
|
{
|
|
memReq = NULL;
|
|
squash(0, 0);
|
|
instBuffer.clear();
|
|
instBufferSize = 0;
|
|
status = Idle;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
FrontEnd<Impl>::takeOverFrom(ExecContext *old_xc)
|
|
{
|
|
assert(freeRegs == numPhysRegs);
|
|
fetchCacheLineNextCycle = true;
|
|
|
|
cacheBlkValid = false;
|
|
|
|
#if !FULL_SYSTEM
|
|
// pTable = params->pTable;
|
|
#endif
|
|
fetchFault = NoFault;
|
|
serializeNext = false;
|
|
barrierInst = NULL;
|
|
status = Running;
|
|
switchedOut = false;
|
|
interruptPending = false;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
FrontEnd<Impl>::dumpInsts()
|
|
{
|
|
cprintf("instBuffer size: %i\n", instBuffer.size());
|
|
|
|
InstBuffIt buff_it = instBuffer.begin();
|
|
|
|
for (int num = 0; buff_it != instBuffer.end(); num++) {
|
|
cprintf("Instruction:%i\nPC:%#x\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
|
|
"Squashed:%i\n\n",
|
|
num, (*buff_it)->readPC(), (*buff_it)->threadNumber,
|
|
(*buff_it)->seqNum, (*buff_it)->isIssued(),
|
|
(*buff_it)->isSquashed());
|
|
buff_it++;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
FrontEnd<Impl>::ICacheCompletionEvent::ICacheCompletionEvent(MemReqPtr &_req, FrontEnd *fe)
|
|
: Event(&mainEventQueue, Delayed_Writeback_Pri), req(_req), frontEnd(fe)
|
|
{
|
|
this->setFlags(Event::AutoDelete);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
FrontEnd<Impl>::ICacheCompletionEvent::process()
|
|
{
|
|
frontEnd->processCacheCompletion(req);
|
|
}
|
|
|
|
template <class Impl>
|
|
const char *
|
|
FrontEnd<Impl>::ICacheCompletionEvent::description()
|
|
{
|
|
return "ICache completion event";
|
|
}
|