8106a80450
arch/SConscript: ev5 should now be contained within alpha specific code. arch/alpha/ev5.cc: arch/alpha/isa_traits.hh: Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed. arch/sparc/isa_traits.hh: Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed. Also made some small fixes. cpu/o3/alpha_cpu.hh: Added typedefs which are required now that there isn't a using namespace EV5. cpu/o3/alpha_cpu_impl.hh: Some small changes so that ev5.hh isn't needed directly. cpu/o3/cpu.hh: Removed including ev5.hh, and pushed retrieving the Asid into the MiscRegFile. cpu/o3/regfile.hh: Removed the include of ev5.hh, using namespace EV5, and the now redundant ipr array. --HG-- extra : convert_revision : 5ef8f69435a3a888a3f06d0095d89326dafb33fd
292 lines
9.2 KiB
C++
292 lines
9.2 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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// Todo: Find all the stuff in ExecContext and ev5 that needs to be
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// specifically designed for this CPU.
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#ifndef __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
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#define __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
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#include "cpu/o3/cpu.hh"
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#include "arch/isa_traits.hh"
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#include "sim/byteswap.hh"
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template <class Impl>
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class AlphaFullCPU : public FullO3CPU<Impl>
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{
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protected:
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typedef TheISA::IntReg IntReg;
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typedef TheISA::MiscReg MiscReg;
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typedef TheISA::RegFile RegFile;
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typedef TheISA::MiscRegFile MiscRegFile;
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public:
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typedef typename Impl::Params Params;
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public:
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AlphaFullCPU(Params ¶ms);
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#if FULL_SYSTEM
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AlphaITB *itb;
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AlphaDTB *dtb;
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#endif
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public:
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void regStats();
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#if FULL_SYSTEM
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//Note that the interrupt stuff from the base CPU might be somewhat
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//ISA specific (ie NumInterruptLevels). These functions might not
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//be needed in FullCPU though.
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// void post_interrupt(int int_num, int index);
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// void clear_interrupt(int int_num, int index);
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// void clear_interrupts();
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Fault translateInstReq(MemReqPtr &req)
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{
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return itb->translate(req);
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}
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Fault translateDataReadReq(MemReqPtr &req)
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{
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return dtb->translate(req, false);
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}
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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return dtb->translate(req, true);
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}
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#else
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Fault dummyTranslation(MemReqPtr &req)
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{
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#if 0
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assert((req->vaddr >> 48 & 0xffff) == 0);
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#endif
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// put the asid in the upper 16 bits of the paddr
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req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
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req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
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return NoFault;
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}
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Fault translateInstReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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Fault translateDataReadReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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#endif
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// Later on may want to remove this misc stuff from the regfile and
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// have it handled at this level. Might prove to be an issue when
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// trying to rename source/destination registers...
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MiscReg readMiscReg(int misc_reg)
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{
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// Dummy function for now.
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// @todo: Fix this once reg file gets fixed.
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return 0;
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}
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Fault setMiscReg(int misc_reg, const MiscReg &val)
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{
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// Dummy function for now.
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// @todo: Fix this once reg file gets fixed.
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return NoFault;
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}
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// Most of the full system code and syscall emulation is not yet
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// implemented. These functions do show what the final interface will
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// look like.
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#if FULL_SYSTEM
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int readIntrFlag();
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void setIntrFlag(int val);
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Fault hwrei();
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bool inPalMode() { return AlphaISA::PcPAL(this->regFile.readPC()); }
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bool inPalMode(uint64_t PC)
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{ return AlphaISA::PcPAL(PC); }
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void trap(Fault fault);
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bool simPalCheck(int palFunc);
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void processInterrupts();
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#endif
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#if !FULL_SYSTEM
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// Need to change these into regfile calls that directly set a certain
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// register. Actually, these functions should handle most of this
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// functionality by themselves; should look up the rename and then
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// set the register.
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IntReg getSyscallArg(int i)
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{
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return this->xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i];
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}
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// used to shift args for indirect syscall
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void setSyscallArg(int i, IntReg val)
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{
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this->xc->regs.intRegFile[AlphaISA::ArgumentReg0 + i] = val;
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}
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void setSyscallReturn(int64_t return_value)
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{
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// check for error condition. Alpha syscall convention is to
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// indicate success/failure in reg a3 (r19) and put the
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// return value itself in the standard return value reg (v0).
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const int RegA3 = 19; // only place this is used
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if (return_value >= 0) {
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// no error
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this->xc->regs.intRegFile[RegA3] = 0;
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this->xc->regs.intRegFile[AlphaISA::ReturnValueReg] = return_value;
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} else {
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// got an error, return details
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this->xc->regs.intRegFile[RegA3] = (IntReg) -1;
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this->xc->regs.intRegFile[AlphaISA::ReturnValueReg] = -return_value;
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}
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}
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void syscall(short thread_num);
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void squashStages();
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#endif
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void copyToXC();
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void copyFromXC();
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public:
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#if FULL_SYSTEM
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bool palShadowEnabled;
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// Not sure this is used anywhere.
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void intr_post(RegFile *regs, Fault fault, Addr pc);
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// Actually used within exec files. Implement properly.
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void swapPALShadow(bool use_shadow);
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// Called by CPU constructor. Can implement as I please.
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void initCPU(RegFile *regs);
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// Called by initCPU. Implement as I please.
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void initIPRs(RegFile *regs);
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void halt() { panic("Halt not implemented!\n"); }
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#endif
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template <class T>
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Fault read(MemReqPtr &req, T &data)
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{
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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if (req->flags & LOCKED) {
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MiscRegFile *cregs = &req->xc->regs.miscRegs;
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cregs->setReg(TheISA::Lock_Addr_DepTag, req->paddr);
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cregs->setReg(TheISA::Lock_Flag_DepTag, true);
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}
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#endif
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Fault error;
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error = this->mem->read(req, data);
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data = gtoh(data);
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return error;
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}
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template <class T>
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Fault read(MemReqPtr &req, T &data, int load_idx)
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{
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return this->iew.ldstQueue.read(req, data, load_idx);
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}
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template <class T>
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Fault write(MemReqPtr &req, T &data)
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{
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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MiscRegFile *cregs;
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// If this is a store conditional, act appropriately
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if (req->flags & LOCKED) {
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cregs = &req->xc->regs.miscRegs;
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if (req->flags & UNCACHEABLE) {
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// Don't update result register (see stq_c in isa_desc)
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req->result = 2;
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req->xc->storeCondFailures = 0;//Needed? [RGD]
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} else {
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bool lock_flag = cregs->readReg(TheISA::Lock_Flag_DepTag);
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Addr lock_addr = cregs->readReg(TheISA::Lock_Addr_DepTag);
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req->result = lock_flag;
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if (!lock_flag ||
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((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
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cregs->setReg(TheISA::Lock_Flag_DepTag, false);
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if (((++req->xc->storeCondFailures) % 100000) == 0) {
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std::cerr << "Warning: "
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<< req->xc->storeCondFailures
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<< " consecutive store conditional failures "
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<< "on cpu " << req->xc->cpu_id
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<< std::endl;
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}
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return NoFault;
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}
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else req->xc->storeCondFailures = 0;
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}
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}
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// Need to clear any locked flags on other proccessors for
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// this address. Only do this for succsful Store Conditionals
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// and all other stores (WH64?). Unsuccessful Store
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// Conditionals would have returned above, and wouldn't fall
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// through.
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for (int i = 0; i < this->system->execContexts.size(); i++){
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cregs = &this->system->execContexts[i]->regs.miscRegs;
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if ((cregs->readReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
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(req->paddr & ~0xf)) {
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cregs->setReg(TheISA::Lock_Flag_DepTag, false);
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}
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}
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#endif
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return this->mem->write(req, (T)htog(data));
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}
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template <class T>
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Fault write(MemReqPtr &req, T &data, int store_idx)
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{
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return this->iew.ldstQueue.write(req, data, store_idx);
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}
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};
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#endif // __CPU_O3_CPU_ALPHA_FULL_CPU_HH__
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