Korey Sewell c32b4ecac1 infinitesimal small baby steps toward MIPS actually working ... arch/mips/isa/formats/branch.isa: let user know that we alter r31 in disassembly arch/mips/isa_traits.cc: add copyRegs function ... comment out serialize float code for now arch/mips/isa_traits.hh: make FloatRegFile a class ... change values of architectural regs arch/mips/process.cc: change MIPS to Mips base/loader/elf_object.cc: get global pointer initialized to a value base/loader/elf_object.hh: Add global_ptr to elf_object constructor base/loader/object_file.hh: MIPS to Mips base/traceflags.py: SimpleCPU trace flag cpu/simple/cpu.cc: DPRINTF flags for SimpleCPU cpu/static_inst.hh: Add Decoder functions to static_inst.hh --HG-- extra : convert_revision : 0544a8524d3fe4229428cb06822f7da208c72459		2006-03-15 16:26:40 -05:00
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alpha	Fixed up after a hand merge.	2006-03-14 16:39:59 -05:00
mips	infinitesimal small baby steps toward MIPS actually working	2006-03-15 16:26:40 -05:00
sparc	Fixed up after a hand merge.	2006-03-14 16:39:59 -05:00
isa_parser.py	Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt.	2006-03-14 15:55:00 -05:00
isa_specific.hh	Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu	2006-03-14 18:28:51 -05:00
SConscript	Moved registerfile.hh to regfile.hh	2006-03-14 16:05:44 -05:00