Jiuyue Ma e1a5522a89 config, x86: Ensure that PCI devs get bridged to the memory bus ... This patch force IO device to be mapped to 0xC0000000-0xFFFF0000 by reserve anything between the end of memory and 3GB if memory is less than 3GB. It also statically bridge these address range to the IO bus, which guaranty access to pci address space will pass though bridge to iobus. Committed by: Nilay Vaish <nilay@cs.wisc.edu>		2014-07-17 12:05:41 +08:00
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Benchmarks.py	configs: add run scripts for ics/gb versions of android and bbench	2012-06-11 11:07:42 -04:00
CacheConfig.py	mem: Rename Bus to XBar to better reflect its behaviour	2014-09-20 17:18:32 -04:00
Caches.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
cpu2000.py	arm: Add support for ARMv8 (AArch64 & AArch32)	2014-01-24 15:29:34 -06:00
CpuConfig.py	cpu: `Minor' in-order CPU model	2014-07-23 16:09:04 -05:00
FSConfig.py	config, x86: Ensure that PCI devs get bridged to the memory bus	2014-07-17 12:05:41 +08:00
MemConfig.py	mem: Rename SimpleDRAM to a more suitable DRAMCtrl	2014-03-23 11:12:12 -04:00
O3_ARM_v7a.py	cpu: Change writeback modeling for outstanding instructions	2014-09-03 07:42:33 -04:00
Options.py	config: add num-work-ids command line option	2014-04-10 13:43:33 -05:00
Simulation.py	config: add num-work-ids command line option	2014-04-10 13:43:33 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00