Mostly just config.ini updates, though the different response latency for bad addresses caused very minor timing changes in the O3 Linux boot tests.
26 lines
813 B
Text
Executable file
26 lines
813 B
Text
Executable file
M5 Simulator System
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Copyright (c) 2001-2008
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The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Apr 21 2009 18:04:32
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M5 revision e6dd09514462 6117 default qtip tip stats-update
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M5 started Apr 21 2009 18:05:08
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M5 executing on zizzer
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command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-atomic
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Global frequency set at 1000000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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Begining test of difficult SPARC instructions...
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LDSTUB: Passed
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SWAP: Passed
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CAS FAIL: Passed
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CAS WORK: Passed
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CASX FAIL: Passed
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CASX WORK: Passed
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LDTX: Passed
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LDTW: Passed
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STTW: Passed
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Done
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Exiting @ tick 7618500 because target called exit()
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