df8df4fd0a
Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller.
1224 lines
140 KiB
Plaintext
1224 lines
140 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.408037 # Number of seconds simulated
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sim_ticks 408037199500 # Number of ticks simulated
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final_tick 408037199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 90640 # Simulator instruction rate (inst/s)
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host_op_rate 111590 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 57729920 # Simulator tick rate (ticks/s)
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host_mem_usage 318440 # Number of bytes of host memory used
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host_seconds 7068.04 # Real time elapsed on the host
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sim_insts 640649298 # Number of instructions simulated
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sim_ops 788724957 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 7008448 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.l2cache.prefetcher 12940608 # Number of bytes read from this memory
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system.physmem.bytes_read::total 20176256 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4244736 # Number of bytes written to this memory
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system.physmem.bytes_written::total 4244736 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 109507 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.l2cache.prefetcher 202197 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 315254 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66324 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 66324 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 556812 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 17176003 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.l2cache.prefetcher 31714285 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 49447099 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 556812 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 556812 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 10402816 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 10402816 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 10402816 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 556812 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 17176003 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.l2cache.prefetcher 31714285 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 59849916 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 315254 # Number of read requests accepted
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system.physmem.writeReqs 66324 # Number of write requests accepted
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system.physmem.readBursts 315254 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 66324 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 20157248 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 19008 # Total number of bytes read from write queue
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system.physmem.bytesWritten 4240064 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 20176256 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 4244736 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 297 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 51 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 14 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 19893 # Per bank write bursts
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system.physmem.perBankRdBursts::1 19507 # Per bank write bursts
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system.physmem.perBankRdBursts::2 19696 # Per bank write bursts
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system.physmem.perBankRdBursts::3 19811 # Per bank write bursts
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system.physmem.perBankRdBursts::4 19755 # Per bank write bursts
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system.physmem.perBankRdBursts::5 20266 # Per bank write bursts
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system.physmem.perBankRdBursts::6 19606 # Per bank write bursts
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system.physmem.perBankRdBursts::7 19431 # Per bank write bursts
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system.physmem.perBankRdBursts::8 19468 # Per bank write bursts
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system.physmem.perBankRdBursts::9 19384 # Per bank write bursts
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system.physmem.perBankRdBursts::10 19414 # Per bank write bursts
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system.physmem.perBankRdBursts::11 19672 # Per bank write bursts
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system.physmem.perBankRdBursts::12 19624 # Per bank write bursts
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system.physmem.perBankRdBursts::13 19992 # Per bank write bursts
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system.physmem.perBankRdBursts::14 19481 # Per bank write bursts
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system.physmem.perBankRdBursts::15 19957 # Per bank write bursts
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system.physmem.perBankWrBursts::0 4278 # Per bank write bursts
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system.physmem.perBankWrBursts::1 4105 # Per bank write bursts
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system.physmem.perBankWrBursts::2 4141 # Per bank write bursts
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system.physmem.perBankWrBursts::3 4152 # Per bank write bursts
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system.physmem.perBankWrBursts::4 4250 # Per bank write bursts
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system.physmem.perBankWrBursts::5 4232 # Per bank write bursts
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system.physmem.perBankWrBursts::6 4174 # Per bank write bursts
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system.physmem.perBankWrBursts::7 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::8 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::9 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::10 4095 # Per bank write bursts
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system.physmem.perBankWrBursts::11 4097 # Per bank write bursts
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system.physmem.perBankWrBursts::12 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::13 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::14 4096 # Per bank write bursts
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system.physmem.perBankWrBursts::15 4151 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 408037145000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 315254 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 66324 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 128804 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 111420 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 14471 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 6711 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 6396 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 7547 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 8690 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 8601 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 7182 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 6341 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 3273 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 2426 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1825 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1270 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 590 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 607 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 986 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 1667 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 2405 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 2934 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 3403 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 3865 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 4344 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 4750 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 5220 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 5565 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 5589 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 5488 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 4554 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 4251 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 4056 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 4042 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 147 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 115 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 95 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 93 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 93 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 90 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 84 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 94 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 85 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 86 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 82 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 77 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 63 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 67 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 9 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 136345 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 178.922586 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 128.860330 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 198.953379 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 53850 39.50% 39.50% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 57322 42.04% 81.54% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 14832 10.88% 92.42% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 1348 0.99% 93.40% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 1343 0.99% 94.39% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1322 0.97% 95.36% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1347 0.99% 96.35% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1288 0.94% 97.29% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 3693 2.71% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 136345 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 4024 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 74.490060 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 34.867874 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 683.746449 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 4004 99.50% 99.50% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 7 0.17% 99.68% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-3071 3 0.07% 99.75% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::3072-4095 2 0.05% 99.80% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::4096-5119 1 0.02% 99.83% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::7168-8191 2 0.05% 99.88% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::8192-9215 2 0.05% 99.93% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.95% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::16384-17407 1 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 4024 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 4024 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.463966 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.422591 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 1.272940 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 3359 83.47% 83.47% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::17 14 0.35% 83.82% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 449 11.16% 94.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 91 2.26% 97.24% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20 36 0.89% 98.14% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::21 19 0.47% 98.61% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::22 14 0.35% 98.96% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::23 17 0.42% 99.38% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::24 8 0.20% 99.58% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::25 6 0.15% 99.73% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::26 4 0.10% 99.83% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::27 5 0.12% 99.95% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 4024 # Writes before turning the bus around for reads
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system.physmem.totQLat 9384520258 # Total ticks spent queuing
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system.physmem.totMemAccLat 15289964008 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 1574785000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 29796.20 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 48546.20 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 49.40 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 49.45 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 10.40 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.47 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.39 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 218395 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 26455 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 69.34 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 39.92 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 1069341.38 # Average gap between requests
|
|
system.physmem.pageHitRate 64.23 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 517708800 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 282480000 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1231869600 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 216613440 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 96151044510 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 160475521500 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 285525816090 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 699.765171 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 266332221673 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 13625040000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 128074629327 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 512870400 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 279840000 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1224147600 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 212693040 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 96078218175 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 160539404250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 285497751705 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 699.696391 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 266439995679 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 13625040000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 127966985321 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 233958621 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 161821709 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 15514987 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 121572023 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 108258061 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 89.048498 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 25035636 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 1300514 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 673 # Number of system calls
|
|
system.cpu.numCycles 816074400 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 84077011 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 1200073954 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 233958621 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 133293697 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 716167787 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 31064641 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 2347 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 2996 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 370071850 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 652472 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 815782492 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.838759 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.161594 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 134746116 16.52% 16.52% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 222503118 27.27% 43.79% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 98075778 12.02% 55.81% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 360457480 44.19% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 815782492 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.286688 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.470545 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 119982553 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 156985722 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 484662665 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 38632910 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 15518642 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 25180928 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 13826 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 1248143840 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 39966741 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 15518642 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 176992343 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 77462427 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 207446 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 464957580 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 80644054 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 1190653894 # Number of instructions processed by rename
|
|
system.cpu.rename.SquashedInsts 25546220 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 24993767 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 2267123 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 40253162 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 1738390 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 1225396904 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 5812470532 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 1358186197 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 40876541 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 350618674 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 7267 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 108147318 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 366118935 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 236099157 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 1781337 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 5349105 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 1168566408 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 12360 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 1017104063 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 18374377 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 379747029 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 1032159170 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 815782492 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.246783 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 258071655 31.63% 31.63% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 228431382 28.00% 59.64% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 215339964 26.40% 86.03% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 97765220 11.98% 98.02% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 16174262 1.98% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 815782492 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 64513595 19.12% 19.12% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 18145 0.01% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.13% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 155496772 46.10% 65.41% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 116668709 34.59% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 456384260 44.87% 44.87% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 5195827 0.51% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.38% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.06% 45.44% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 322085949 31.67% 78.80% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 215583681 21.20% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 1017104063 # Type of FU issued
|
|
system.cpu.iq.rate 1.246337 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 337334110 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.331661 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 3143822052 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 1504778489 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 934283929 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 61877053 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 43565817 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 1320627818 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 33810355 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 9960647 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 113877997 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 1254 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 18512 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 107118661 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2065827 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 22129 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 15518642 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 35326933 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 672265 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 1168584324 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 366118935 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 236099157 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 6620 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 110 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 675878 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 18512 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 15437821 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 3784778 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 19222599 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 974764839 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 303299768 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 42339224 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 5556 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 497763810 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 150614661 # Number of branches executed
|
|
system.cpu.iew.exec_stores 194464042 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.194456 # Inst execution rate
|
|
system.cpu.iew.wb_sent 963735760 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 960436373 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 536684839 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 893296754 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.176898 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.600791 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 357425480 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 15501309 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 764959828 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.031074 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.790810 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 428887379 56.07% 56.07% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 171843268 22.46% 78.53% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 73566556 9.62% 88.15% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 31622898 4.13% 92.28% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 7902308 1.03% 93.32% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 14889162 1.95% 95.26% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 7268582 0.95% 96.21% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 6618939 0.87% 97.08% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 22360736 2.92% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 764959828 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 640654410 # Number of instructions committed
|
|
system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 381221434 # Number of memory references committed
|
|
system.cpu.commit.loads 252240938 # Number of loads committed
|
|
system.cpu.commit.membars 5740 # Number of memory barriers committed
|
|
system.cpu.commit.branches 137364859 # Number of branches committed
|
|
system.cpu.commit.fp_insts 24239771 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 682251399 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 19275340 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 385756793 48.91% 48.91% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 22360736 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 1888745890 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 2343137518 # The number of ROB writes
|
|
system.cpu.timesIdled 647360 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 291908 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 640649298 # Number of Instructions Simulated
|
|
system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 1.273824 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 1.273824 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.785038 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.785038 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 995816176 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 567918829 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 31889844 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 3794477294 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 384905750 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 715814324 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes
|
|
system.cpu.dcache.tags.replacements 2756166 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.936576 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 414250087 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 2756678 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 150.271481 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 246939500 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.936576 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999876 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999876 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 189 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 839347788 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 839347788 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 286297988 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 286297988 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 127937398 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 127937398 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 3156 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 3156 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 414235386 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 414235386 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 414238542 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 414238542 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 3030809 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 3030809 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1014079 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1014079 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 4044888 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 4044888 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 4045534 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 4045534 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 33766010929 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 33766010929 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 9872401734 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 9872401734 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 175500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 175500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 43638412663 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 43638412663 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 43638412663 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 43638412663 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 289328797 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 289328797 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3802 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 3802 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 418280274 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 418280274 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 418284076 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 418284076 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010475 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.010475 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007864 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.007864 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169911 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.169911 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.009670 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.009670 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.009672 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.009672 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11140.923407 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 11140.923407 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9735.337912 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 9735.337912 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58500 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 10788.534235 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 10788.534235 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 10786.811497 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 10786.811497 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 383706 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 5260 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 72.947909 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 735128 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 735128 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 995619 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 995619 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 293215 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 293215 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1288834 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1288834 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1288834 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1288834 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035190 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 2035190 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720864 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 720864 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 2756054 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 2756054 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 2756695 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 2756695 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21052594116 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 21052594116 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5256752100 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5256752100 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5684476 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5684476 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26309346216 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 26309346216 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26315030692 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 26315030692 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168595 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168595 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006590 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.006590 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10344.289288 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10344.289288 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7292.293831 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7292.293831 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8868.137285 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8868.137285 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9546.019859 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 9546.019859 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9545.862234 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 9545.862234 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 5169210 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 510.721915 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 364899992 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 5169720 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 70.584092 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 237857250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.721915 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.997504 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.997504 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 745313375 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 745313375 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 364900028 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 364900028 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 364900028 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 364900028 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 364900028 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 364900028 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 5171791 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 5171791 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 5171791 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 5171791 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 5171791 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 5171791 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 41611685167 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 41611685167 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 41611685167 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 41611685167 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 41611685167 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 41611685167 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 370071819 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 370071819 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 370071819 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 370071819 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 370071819 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 370071819 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013975 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.013975 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.013975 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.013975 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.013975 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.013975 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8045.894578 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 8045.894578 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8045.894578 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 8045.894578 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8045.894578 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 8045.894578 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 67339 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 39 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 2239 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 30.075480 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets 9.750000 # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2054 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 2054 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 2054 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 2054 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 2054 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 2054 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169737 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 5169737 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 5169737 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 5169737 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 5169737 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 5169737 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33819004202 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 33819004202 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33819004202 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 33819004202 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33819004202 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 33819004202 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6541.726243 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6541.726243 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6541.726243 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 6541.726243 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6541.726243 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 6541.726243 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.prefetcher.num_hwpf_issued 1345350 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.pfIdentified 1355301 # number of prefetch candidates identified
|
|
system.cpu.l2cache.prefetcher.pfBufferHit 8714 # number of redundant prefetches already in prefetch queue
|
|
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
|
|
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
|
|
system.cpu.l2cache.prefetcher.pfSpanPage 4790331 # number of prefetches not generated due to page crossing
|
|
system.cpu.l2cache.tags.replacements 298968 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 16361.863198 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 7823723 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 315332 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 24.811066 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 13372026000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 741.351492 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 129.669964 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 8767.936523 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6722.905220 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.045249 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007914 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.535152 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.410334 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.998649 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1022 6534 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 9830 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1473 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4885 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2092 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7253 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.398804 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.599976 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 139620886 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 139620886 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 5166160 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1926359 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 7092519 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 735128 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 735128 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 717996 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 717996 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 5166160 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 2644355 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 7810515 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 5166160 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 2644355 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 7810515 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3561 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 109472 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 113033 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 14 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 2851 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 2851 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3561 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 112323 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 115884 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3561 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 112323 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 115884 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 237049229 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7458222067 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 7695271296 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 224011514 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 224011514 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 237049229 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7682233581 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 7919282810 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 237049229 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7682233581 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 7919282810 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 5169721 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 2035831 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 7205552 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 735128 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 735128 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 5169721 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 2756678 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 7926399 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 5169721 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 2756678 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 7926399 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.053773 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.015687 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823529 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823529 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003955 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.003955 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.040746 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.014620 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.040746 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.014620 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66568.163156 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68129.038174 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68079.864252 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78572.961768 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78572.961768 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66568.163156 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68394.127481 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 68338.017414 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66568.163156 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68394.127481 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 68338.017414 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66324 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66324 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1342 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 1353 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1474 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::total 1474 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 2816 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 2827 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 2816 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 2827 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3550 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108130 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 111680 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202272 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::total 202272 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1377 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1377 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3550 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 109507 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 113057 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3550 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 109507 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202272 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 315329 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205967021 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6469574626 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6675541647 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18462254833 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18462254833 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 84014 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 84014 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126131000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126131000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205967021 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6595705626 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 6801672647 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205967021 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6595705626 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18462254833 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 25263927480 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053113 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015499 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823529 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823529 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.039782 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58018.879155 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59831.449422 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59773.832799 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91274.397015 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91598.402324 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91598.402324 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58018.879155 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60161.446412 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58018.879155 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80119.264261 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 7205568 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 7205568 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 735128 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFReq 316987 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10339458 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248518 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 16587976 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330862144 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223475584 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 554337728 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 317003 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 8978547 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 5.035305 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.184549 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::5 8661560 96.47% 96.47% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::6 316987 3.53% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 8978547 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 5065908000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 7755114990 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 4143326908 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadReq 313877 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 313877 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 66324 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 14 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 14 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 1377 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 1377 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 696860 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 696860 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24420992 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 24420992 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 381592 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 381592 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 381592 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 993954700 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2896150900 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
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