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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
Andreas Hansson df8df4fd0a stats: Bump stats for decoder, TLB, prefetcher and DRAM changes 
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
2014-12-23 09:31:20 -05:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.825254 # Number of seconds simulated
sim_ticks 2825254262000 # Number of ticks simulated
final_tick 2825254262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 94727 # Simulator instruction rate (inst/s)
host_op_rate 114921 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2228089891 # Simulator tick rate (ticks/s)
host_mem_usage 647304 # Number of bytes of host memory used
host_seconds 1268.02 # Real time elapsed on the host
sim_insts 120114928 # Number of instructions simulated
sim_ops 145721614 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1295328 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 1287356 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 8203456 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 192592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 613216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 685312 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 12280396 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1295328 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 192592 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1487920 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8689216 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
system.physmem.bytes_written::total 8706960 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 22485 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 20640 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 128179 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 3076 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 9605 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 10708 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 194742 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 135769 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
system.physmem.num_writes::total 140205 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 566 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 458482 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 455660 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 2903617 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 113 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 68168 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 217048 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 242566 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4346652 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 458482 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 68168 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 526650 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3075552 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6266 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3081832 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3075552 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 566 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 458482 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 461927 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 2903617 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 68168 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 217062 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 242566 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7428484 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 194742 # Number of read requests accepted
system.physmem.writeReqs 176429 # Number of write requests accepted
system.physmem.readBursts 194742 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 176429 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 12454272 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue
system.physmem.bytesWritten 10909824 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 12280396 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 11025296 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 5937 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 13544 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 12112 # Per bank write bursts
system.physmem.perBankRdBursts::1 11748 # Per bank write bursts
system.physmem.perBankRdBursts::2 12331 # Per bank write bursts
system.physmem.perBankRdBursts::3 12396 # Per bank write bursts
system.physmem.perBankRdBursts::4 14329 # Per bank write bursts
system.physmem.perBankRdBursts::5 12174 # Per bank write bursts
system.physmem.perBankRdBursts::6 12464 # Per bank write bursts
system.physmem.perBankRdBursts::7 12653 # Per bank write bursts
system.physmem.perBankRdBursts::8 12280 # Per bank write bursts
system.physmem.perBankRdBursts::9 12648 # Per bank write bursts
system.physmem.perBankRdBursts::10 12320 # Per bank write bursts
system.physmem.perBankRdBursts::11 11195 # Per bank write bursts
system.physmem.perBankRdBursts::12 11560 # Per bank write bursts
system.physmem.perBankRdBursts::13 11958 # Per bank write bursts
system.physmem.perBankRdBursts::14 11562 # Per bank write bursts
system.physmem.perBankRdBursts::15 10868 # Per bank write bursts
system.physmem.perBankWrBursts::0 10717 # Per bank write bursts
system.physmem.perBankWrBursts::1 10772 # Per bank write bursts
system.physmem.perBankWrBursts::2 11107 # Per bank write bursts
system.physmem.perBankWrBursts::3 11182 # Per bank write bursts
system.physmem.perBankWrBursts::4 10467 # Per bank write bursts
system.physmem.perBankWrBursts::5 10805 # Per bank write bursts
system.physmem.perBankWrBursts::6 10968 # Per bank write bursts
system.physmem.perBankWrBursts::7 10867 # Per bank write bursts
system.physmem.perBankWrBursts::8 10652 # Per bank write bursts
system.physmem.perBankWrBursts::9 11077 # Per bank write bursts
system.physmem.perBankWrBursts::10 11118 # Per bank write bursts
system.physmem.perBankWrBursts::11 10634 # Per bank write bursts
system.physmem.perBankWrBursts::12 10720 # Per bank write bursts
system.physmem.perBankWrBursts::13 10162 # Per bank write bursts
system.physmem.perBankWrBursts::14 9784 # Per bank write bursts
system.physmem.perBankWrBursts::15 9434 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
system.physmem.totGap 2825253981000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 559 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 3083 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 191072 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4436 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 171993 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 63499 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 64318 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 19752 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 11777 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8456 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 7342 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 6123 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 5234 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 4663 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1232 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 932 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 716 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 303 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 246 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2802 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 4429 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 5695 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6931 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 7739 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 9144 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 10091 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 11254 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 11401 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 12403 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 11881 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 11813 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 11317 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 11573 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 9596 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 9235 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 9000 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 8434 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 981 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 722 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 557 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 418 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 349 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 303 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 269 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 206 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 211 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 182 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 96 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 89336 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 261.529865 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 143.433799 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 324.548299 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 46507 52.06% 52.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 17145 19.19% 71.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5910 6.62% 77.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3229 3.61% 81.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2663 2.98% 84.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1401 1.57% 86.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 977 1.09% 87.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1056 1.18% 88.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 10448 11.70% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 89336 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 7194 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 27.049903 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 528.366464 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 7192 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 7194 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 7194 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 23.695580 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 20.063476 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 21.872294 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-23 6078 84.49% 84.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-31 276 3.84% 88.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-39 196 2.72% 91.05% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-47 78 1.08% 92.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-55 140 1.95% 94.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-63 36 0.50% 94.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-71 37 0.51% 95.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-79 44 0.61% 95.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-87 68 0.95% 96.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-95 17 0.24% 96.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-103 97 1.35% 98.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-111 14 0.19% 98.43% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-119 17 0.24% 98.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-127 12 0.17% 98.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-135 42 0.58% 99.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-143 4 0.06% 99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-151 10 0.14% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-159 3 0.04% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-167 8 0.11% 99.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-183 4 0.06% 99.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-191 1 0.01% 99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-199 1 0.01% 99.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-207 2 0.03% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::216-223 2 0.03% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-231 2 0.03% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::232-239 1 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::240-247 1 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::248-255 1 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::256-263 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-343 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 7194 # Writes before turning the bus around for reads
system.physmem.totQLat 6681295250 # Total ticks spent queuing
system.physmem.totMemAccLat 10330007750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 972990000 # Total ticks spent in databus transfers
system.physmem.avgQLat 34333.83 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 53083.83 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.35 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 26.38 # Average write queue length when enqueuing
system.physmem.readRowHits 162654 # Number of row buffer hits during reads
system.physmem.writeRowHits 113073 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.58 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 66.32 # Row buffer hit rate for writes
system.physmem.avgGap 7611731.47 # Average gap between requests
system.physmem.pageHitRate 75.52 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 347571000 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 189646875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 781614600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 563014800 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 184531504560 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 79272493785 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1625612031750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1891297877370 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.427007 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2704246406250 # Time in different power states
system.physmem_0.memoryStateTime::REF 94341260000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 26661192500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 327809160 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 178864125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 736242000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 541604880 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 184531504560 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 78684430770 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1626127876500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1891128331995 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.366996 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2705112983500 # Time in different power states
system.physmem_1.memoryStateTime::REF 94341260000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 25799982000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 23750953 # Number of BP lookups
system.cpu0.branchPred.condPredicted 15527618 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 965372 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 14472059 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 10661692 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 73.670872 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 3843618 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 32002 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 61986 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 61986 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26264 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18370 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 17352 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 44634 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 336.413945 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 2220.174334 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-8191 43963 98.50% 98.50% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::8192-16383 507 1.14% 99.63% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-24575 73 0.16% 99.80% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-32767 64 0.14% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-40959 21 0.05% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::40960-49151 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 44634 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 13427 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 7972.648842 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 6416.497879 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 8239.915942 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-32767 13383 99.67% 99.67% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-65535 25 0.19% 99.86% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.87% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-163839 6 0.04% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::163840-196607 10 0.07% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 13427 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 89356407948 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.591290 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.497127 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 36606156956 40.97% 40.97% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::1 52714291992 58.99% 99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2 18812000 0.02% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::3 8121500 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4 2346000 0.00% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::5 1919500 0.00% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6 1535000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::7 979500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8 384000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::9 515500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10 241000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::11 224500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12 422000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::13 109500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14 86500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::15 262500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 89356407948 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 4894 78.56% 78.56% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1336 21.44% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 6230 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 61986 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 61986 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6230 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6230 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 68216 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 17554590 # DTB read hits
system.cpu0.dtb.read_misses 54209 # DTB read misses
system.cpu0.dtb.write_hits 14392399 # DTB write hits
system.cpu0.dtb.write_misses 7777 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 317 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 2330 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 789 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 17608799 # DTB read accesses
system.cpu0.dtb.write_accesses 14400176 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 31946989 # DTB hits
system.cpu0.dtb.misses 61986 # DTB misses
system.cpu0.dtb.accesses 32008975 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 10002 # Table walker walks requested
system.cpu0.itb.walker.walksShort 10002 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3947 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5990 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 65 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 9937 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 314.380598 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 1718.762352 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-2047 9514 95.74% 95.74% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::2048-4095 89 0.90% 96.64% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::4096-6143 92 0.93% 97.56% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::6144-8191 156 1.57% 99.13% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-10239 23 0.23% 99.37% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::10240-12287 21 0.21% 99.58% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::12288-14335 10 0.10% 99.68% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::14336-16383 9 0.09% 99.77% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-18431 7 0.07% 99.84% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::18432-20479 4 0.04% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::20480-22527 2 0.02% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::22528-24575 4 0.04% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-26623 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::26624-28671 3 0.03% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::28672-30719 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 9937 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 2600 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 9117.887308 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 7551.234816 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 5655.414847 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191 1525 58.65% 58.65% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383 976 37.54% 96.19% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575 32 1.23% 97.42% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767 60 2.31% 99.73% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959 5 0.19% 99.92% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 2600 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 20627596212 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.981751 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.134001 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 376836000 1.83% 1.83% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 20250383712 98.17% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 360000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 16500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 20627596212 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 2218 87.50% 87.50% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 317 12.50% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2535 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10002 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10002 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2535 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2535 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 12537 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 37321844 # ITB inst hits
system.cpu0.itb.inst_misses 10002 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2308 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 1915 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 37331846 # ITB inst accesses
system.cpu0.itb.hits 37321844 # DTB hits
system.cpu0.itb.misses 10002 # DTB misses
system.cpu0.itb.accesses 37331846 # DTB accesses
system.cpu0.numCycles 127490392 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 18416586 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 111347815 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 23750953 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 14505310 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 103542853 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 2791794 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 127823 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 53549 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 359263 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 418714 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 68477 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 37322509 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 269100 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 3836 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 124383162 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.079346 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.261981 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 62596919 50.33% 50.33% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 21226112 17.07% 67.39% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 8654044 6.96% 74.35% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 31906087 25.65% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 124383162 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.186296 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.873382 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 19346102 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 58140113 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 40971754 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 4869688 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1055505 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 3027271 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 344448 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 109400605 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 3934770 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1055505 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 25005985 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 11977086 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 36202111 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 40046327 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 10096148 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 104386948 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 1045357 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 1411792 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 159433 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 59086 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 5966912 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 108436619 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 476371377 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 119317721 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 9226 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 97033193 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 11403415 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1211111 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 1071444 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 12097609 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 18549268 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 15931724 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1681801 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 2123013 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 101474466 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1673346 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 99505309 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 475979 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 8870309 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 22101778 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 120255 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 124383162 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.799990 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.034146 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 68905319 55.40% 55.40% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 22874220 18.39% 73.79% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 22288669 17.92% 91.71% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 9206102 7.40% 99.11% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1108815 0.89% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 37 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 124383162 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 9283826 40.69% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 70 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.69% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 5520798 24.20% 64.89% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 8011764 35.11% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 2266 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 65682798 66.01% 66.01% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 92825 0.09% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.10% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 8012 0.01% 66.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 18253823 18.34% 84.46% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 15465584 15.54% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 99505309 # Type of FU issued
system.cpu0.iq.rate 0.780493 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 22816458 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.229299 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 346654844 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 112025701 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 97442801 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 31372 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 11049 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 9514 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 122299120 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 20381 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 360751 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 1973339 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2498 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 18704 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 1001610 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 104951 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 329906 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 1055505 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 1579113 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 185823 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 103314574 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 18549268 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 15931724 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 862014 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 26297 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 136520 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 18704 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 287591 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 395520 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 683111 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 98423737 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 17803606 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1019712 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 166762 # number of nop insts executed
system.cpu0.iew.exec_refs 33081779 # number of memory reference insts executed
system.cpu0.iew.exec_branches 16674739 # Number of branches executed
system.cpu0.iew.exec_stores 15278173 # Number of stores executed
system.cpu0.iew.exec_rate 0.772009 # Inst execution rate
system.cpu0.iew.wb_sent 97898733 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 97452315 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 50771632 # num instructions producing a value
system.cpu0.iew.wb_consumers 83764488 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 0.764389 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.606124 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 8390139 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 1553091 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 624980 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 122653513 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.765118 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.477688 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 78804860 64.25% 64.25% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 24438835 19.93% 84.18% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 8183554 6.67% 90.85% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 3164514 2.58% 93.43% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 3412948 2.78% 96.21% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 1509244 1.23% 97.44% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 1121963 0.91% 98.36% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 525683 0.43% 98.78% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1491912 1.22% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 122653513 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 78072085 # Number of instructions committed
system.cpu0.commit.committedOps 93844352 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 31506042 # Number of memory references committed
system.cpu0.commit.loads 16575928 # Number of loads committed
system.cpu0.commit.membars 642248 # Number of memory barriers committed
system.cpu0.commit.branches 16047033 # Number of branches committed
system.cpu0.commit.fp_insts 9500 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 80932371 # Number of committed integer instructions.
system.cpu0.commit.function_calls 1914804 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 62239958 66.32% 66.32% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 90340 0.10% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.42% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 8012 0.01% 66.43% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.43% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.43% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.43% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 16575928 17.66% 84.09% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 14930114 15.91% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 93844352 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1491912 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 219244998 # The number of ROB reads
system.cpu0.rob.rob_writes 206197797 # The number of ROB writes
system.cpu0.timesIdled 126478 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 3107230 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 5523018391 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 77956509 # Number of Instructions Simulated
system.cpu0.committedOps 93728776 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.635404 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.635404 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.611470 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.611470 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 109237443 # number of integer regfile reads
system.cpu0.int_regfile_writes 59093647 # number of integer regfile writes
system.cpu0.fp_regfile_reads 8049 # number of floating regfile reads
system.cpu0.fp_regfile_writes 2136 # number of floating regfile writes
system.cpu0.cc_regfile_reads 346833598 # number of cc regfile reads
system.cpu0.cc_regfile_writes 40564465 # number of cc regfile writes
system.cpu0.misc_regfile_reads 243214174 # number of misc regfile reads
system.cpu0.misc_regfile_writes 1207250 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 702516 # number of replacements
system.cpu0.dcache.tags.tagsinuse 497.143728 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 28480758 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 703028 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 40.511556 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 256726000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.143728 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970984 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.970984 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 62650967 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 62650967 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 15440226 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 15440226 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 11830536 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 11830536 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306667 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 306667 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 359893 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 359893 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 358331 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 358331 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 27270762 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 27270762 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 27577429 # number of overall hits
system.cpu0.dcache.overall_hits::total 27577429 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 630655 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 630655 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1827082 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1827082 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147933 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 147933 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25364 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 25364 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20059 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 20059 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2457737 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2457737 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2605670 # number of overall misses
system.cpu0.dcache.overall_misses::total 2605670 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8272706723 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 8272706723 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25439418868 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 25439418868 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 389472743 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 389472743 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 444610334 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 444610334 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 421500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 421500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 33712125591 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 33712125591 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 33712125591 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 33712125591 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 16070881 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 16070881 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 13657618 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 13657618 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 454600 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 454600 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 385257 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 385257 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 378390 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 378390 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 29728499 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 29728499 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 30183099 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 30183099 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039242 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.039242 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.133778 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.133778 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325414 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325414 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065837 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065837 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053011 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053011 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082673 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.082673 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086329 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.086329 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13117.642329 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13117.642329 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13923.523338 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 13923.523338 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15355.336027 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15355.336027 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22165.129568 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22165.129568 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13716.734374 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13716.734374 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12937.987386 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 12937.987386 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 953 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 3495034 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 56 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 184351 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.017857 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 18.958584 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 508420 # number of writebacks
system.cpu0.dcache.writebacks::total 508420 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 245938 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 245938 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1508738 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1508738 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18883 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18883 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1754676 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1754676 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1754676 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1754676 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 384717 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 384717 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 318344 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 318344 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102343 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 102343 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6481 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6481 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20059 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 20059 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 703061 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 703061 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 805404 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 805404 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4089649462 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4089649462 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4952590494 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4952590494 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1562592504 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1562592504 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94643501 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94643501 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 403849666 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 403849666 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 399500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 399500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9042239956 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 9042239956 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10604832460 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 10604832460 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4215061000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4215061000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3183836000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3183836000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7398897000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7398897000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023939 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023939 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023309 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023309 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225128 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225128 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016823 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016823 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053011 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053011 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023649 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.023649 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026684 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.026684 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10630.280081 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10630.280081 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15557.354604 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15557.354604 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15268.191317 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15268.191317 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14603.224965 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14603.224965 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20133.090682 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20133.090682 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12861.245263 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12861.245263 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13167.096836 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13167.096836 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 1252930 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.771234 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 36023030 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1253442 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 28.739287 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6360261750 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.771234 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999553 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999553 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 133 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 75891509 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 75891509 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 36023030 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 36023030 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 36023030 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 36023030 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 36023030 # number of overall hits
system.cpu0.icache.overall_hits::total 36023030 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1295987 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1295987 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1295987 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1295987 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1295987 # number of overall misses
system.cpu0.icache.overall_misses::total 1295987 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12767063333 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 12767063333 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 12767063333 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 12767063333 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 12767063333 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 12767063333 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 37319017 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 37319017 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 37319017 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 37319017 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 37319017 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 37319017 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034727 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.034727 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034727 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.034727 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034727 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.034727 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9851.227931 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 9851.227931 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9851.227931 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 9851.227931 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9851.227931 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 9851.227931 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 1314207 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 320 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 107284 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.249795 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 42511 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 42511 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 42511 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 42511 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 42511 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 42511 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1253476 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1253476 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 1253476 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1253476 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 1253476 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1253476 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10355026178 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 10355026178 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10355026178 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 10355026178 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10355026178 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 10355026178 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243898498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 243898498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 243898498 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 243898498 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033588 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033588 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033588 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.033588 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033588 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.033588 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8261.048618 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8261.048618 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8261.048618 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 8261.048618 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8261.048618 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 8261.048618 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1786740 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 1791804 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 4513 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 232652 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 271541 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16114.824240 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 2179855 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 287784 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 7.574622 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 7401.476938 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.779155 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.071208 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5022.663817 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1991.190162 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1686.642960 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.451750 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000780 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.306559 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.121533 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.102945 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.983571 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1106 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15123 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 20 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 157 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 467 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 462 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4242 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5796 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4505 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.067505 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.923035 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 43185169 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 43185169 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 51927 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 11921 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1199916 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.data 396490 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 1660254 # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks 508419 # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total 508419 # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28435 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 28435 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1750 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 1750 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 214572 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 214572 # number of ReadExReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 51927 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 11921 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1199916 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 611062 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 1874826 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 51927 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 11921 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1199916 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 611062 # number of overall hits
system.cpu0.l2cache.overall_hits::total 1874826 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 385 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 135 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.inst 53537 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.data 96948 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 151005 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26067 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 26067 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18308 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 18308 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 49454 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 49454 # number of ReadExReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 385 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 135 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 53537 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 146402 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 200459 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 385 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 135 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 53537 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 146402 # number of overall misses
system.cpu0.l2cache.overall_misses::total 200459 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10304000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3078250 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2513333739 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2834189427 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 5360905416 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 466106536 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 466106536 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 359161772 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 359161772 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 388500 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 388500 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2526024290 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 2526024290 # number of ReadExReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10304000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3078250 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2513333739 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 5360213717 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 7886929706 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10304000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3078250 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2513333739 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 5360213717 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 7886929706 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 52312 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12056 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1253453 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.data 493438 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 1811259 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks 508419 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total 508419 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54502 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 54502 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20058 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 20058 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 264026 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 264026 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 52312 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12056 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1253453 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 757464 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 2075285 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 52312 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12056 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1253453 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 757464 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 2075285 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007360 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.011198 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.042712 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.196475 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.083370 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.478276 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.478276 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.912753 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.912753 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.187307 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.187307 # miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007360 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.011198 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042712 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.193279 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.096593 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007360 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.011198 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042712 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.193279 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.096593 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26763.636364 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22801.851852 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46945.733586 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29234.119600 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35501.509328 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17881.096252 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17881.096252 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19617.750273 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19617.750273 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 388500 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 388500 # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 51078.260404 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 51078.260404 # average ReadExReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26763.636364 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22801.851852 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46945.733586 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36612.981496 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 39344.353239 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26763.636364 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22801.851852 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46945.733586 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36612.981496 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 39344.353239 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 16.250000 # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks 194082 # number of writebacks
system.cpu0.l2cache.writebacks::total 194082 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 2 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 32 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 822 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 857 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 7903 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 7903 # number of ReadExReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 2 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 32 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 8725 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 8760 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 2 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 32 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 8725 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 8760 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 383 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 134 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 53505 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 96126 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 150148 # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 239164 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 239164 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26067 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26067 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18308 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18308 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41551 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 41551 # number of ReadExReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 383 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 134 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 53505 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137677 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 191699 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 383 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 134 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 53505 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137677 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 239164 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 430863 # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 7587500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2127750 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2131132759 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2116031933 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4256879942 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14990297637 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14990297637 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 447102942 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 447102942 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 245146796 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 245146796 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 311500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 311500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1512200931 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1512200931 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7587500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2127750 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2131132759 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3628232864 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 5769080873 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7587500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2127750 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2131132759 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3628232864 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14990297637 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 20759378510 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218480000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4052038481 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4270518481 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3037285940 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3037285940 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218480000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7089324421 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7307804421 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007321 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011115 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042686 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.194809 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.082897 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.478276 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.478276 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.912753 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.912753 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157375 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157375 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007321 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.011115 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042686 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181760 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.092372 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007321 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.011115 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042686 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181760 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.207616 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39830.534698 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22013.107099 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28351.226403 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62677.901511 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 62677.901511 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17152.067442 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17152.067442 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13390.146166 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13390.146166 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 311500 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 311500 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36393.851676 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36393.851676 # average ReadExReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39830.534698 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 26353.224315 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30094.475574 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39830.534698 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 26353.224315 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62677.901511 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48180.926443 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq 1959682 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1897898 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 19079 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 19079 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback 508419 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 329547 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp 131 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 88597 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42717 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 112274 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 292255 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 279169 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2512932 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2353027 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27983 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 115316 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 5009258 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80268960 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 85221321 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 48224 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 209248 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 165747753 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 677561 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 3234113 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 5.173543 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.378716 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::5 2672856 82.65% 82.65% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::6 561257 17.35% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 3234113 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 1876283497 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 114853000 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 1888093495 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 1210751284 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 15934735 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 63036190 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 34134097 # Number of BP lookups
system.cpu1.branchPred.condPredicted 11727075 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 316019 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 18898892 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 15069568 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 79.737839 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 12517859 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 7561 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 23600 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 23600 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8914 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6871 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 7815 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 15785 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 672.093760 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 3265.172364 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-4095 14984 94.93% 94.93% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::4096-8191 394 2.50% 97.42% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::8192-12287 71 0.45% 97.87% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::12288-16383 205 1.30% 99.17% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-20479 14 0.09% 99.26% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::20480-24575 30 0.19% 99.45% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-28671 46 0.29% 99.74% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::28672-32767 19 0.12% 99.86% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-36863 16 0.10% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::45056-49151 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-53247 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 15785 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 5984 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 7948.780916 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 6651.023666 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 5565.886785 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191 4665 77.96% 77.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383 897 14.99% 92.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575 299 5.00% 97.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767 93 1.55% 99.50% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959 7 0.12% 99.62% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151 21 0.35% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-106495 2 0.03% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 5984 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 71907287764 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.149161 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.363512 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 61231753172 85.15% 85.15% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 10656881592 14.82% 99.97% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2 10600500 0.01% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::3 3048000 0.00% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4 1243000 0.00% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::5 909500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6 707500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::7 390500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8 165000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::9 220500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10 87000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::11 114500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12 127500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::13 62500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14 410000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::15 567000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 71907287764 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 2101 76.21% 76.21% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 656 23.79% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 2757 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 23600 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 23600 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2757 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2757 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 26357 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 10322903 # DTB read hits
system.cpu1.dtb.read_misses 19223 # DTB read misses
system.cpu1.dtb.write_hits 6788033 # DTB write hits
system.cpu1.dtb.write_misses 4377 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 2089 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 54 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 392 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 398 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 10342126 # DTB read accesses
system.cpu1.dtb.write_accesses 6792410 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 17110936 # DTB hits
system.cpu1.dtb.misses 23600 # DTB misses
system.cpu1.dtb.accesses 17134536 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 7135 # Table walker walks requested
system.cpu1.itb.walker.walksShort 7135 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4170 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2894 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 71 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 7064 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 161.877123 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 1382.094776 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-2047 6918 97.93% 97.93% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::2048-4095 45 0.64% 98.57% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::4096-6143 37 0.52% 99.09% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::6144-8191 22 0.31% 99.41% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-10239 14 0.20% 99.60% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::10240-12287 9 0.13% 99.73% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::12288-14335 4 0.06% 99.79% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::14336-16383 3 0.04% 99.83% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::18432-20479 2 0.03% 99.86% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::20480-22527 1 0.01% 99.87% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::22528-24575 2 0.03% 99.90% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-26623 4 0.06% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::26624-28671 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::28672-30719 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 7064 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 1280 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 9064.455469 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 7676.805908 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 5570.114480 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-4095 198 15.47% 15.47% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191 721 56.33% 71.80% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287 25 1.95% 73.75% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383 272 21.25% 95.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479 5 0.39% 95.39% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575 10 0.78% 96.17% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.64% 97.81% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.48% 99.30% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.08% 99.37% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959 6 0.47% 99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.08% 99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.08% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 1280 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 16042620916 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.990716 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.095951 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 149006264 0.93% 0.93% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 15893540152 99.07% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 74500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 16042620916 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 1033 85.44% 85.44% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 176 14.56% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 1209 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7135 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7135 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1209 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1209 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 8344 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 43998995 # ITB inst hits
system.cpu1.itb.inst_misses 7135 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 1239 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 569 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 44006130 # ITB inst accesses
system.cpu1.itb.hits 43998995 # DTB hits
system.cpu1.itb.misses 7135 # DTB misses
system.cpu1.itb.accesses 44006130 # DTB accesses
system.cpu1.numCycles 106356723 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 10248604 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 110247468 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 34134097 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 27587427 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 92894950 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3804096 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 79886 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 35043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 199386 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 306315 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 18555 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 43998345 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 120822 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 2367 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 105684787 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.292794 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.339203 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 48118877 45.53% 45.53% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 14213464 13.45% 58.98% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 7642144 7.23% 66.21% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 35710302 33.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 105684787 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.320940 # Number of branch fetches per cycle
system.cpu1.fetch.rate 1.036582 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 13299736 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 62299682 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 27136759 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 1184524 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1764086 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 778297 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 140897 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 69265057 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 1207807 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 1764086 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 17799261 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 2243721 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 57294733 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 23798018 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 2784968 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 56317455 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 239325 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 267963 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 37417 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 15706 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 1709289 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 56195584 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 266063253 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 60158486 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 1810 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 53296548 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 2899036 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 1893782 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 1819648 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 13269922 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 10622155 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 7171113 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 643276 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 895479 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 55388735 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 607798 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 55019063 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 118019 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 2383882 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 6031867 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 50125 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 105684787 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.520596 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 0.855641 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 71804994 67.94% 67.94% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 16804413 15.90% 83.84% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 13307202 12.59% 96.43% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 3472478 3.29% 99.72% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 295688 0.28% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 105684787 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 3013223 44.49% 44.49% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 670 0.01% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.50% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 1729221 25.53% 70.03% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 2029703 29.97% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 73 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 37421348 68.02% 68.02% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 46238 0.08% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.10% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 3333 0.01% 68.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 10544210 19.16% 87.27% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 7003861 12.73% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 55019063 # Type of FU issued
system.cpu1.iq.rate 0.517307 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 6772817 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.123099 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 222607082 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 58388753 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 53008185 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 6667 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 2258 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 1929 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 61787450 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 4357 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 94839 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 509093 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 756 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 10627 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 368944 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 52621 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 79740 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 1764086 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 541667 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 103172 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 56056220 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 10622155 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 7171113 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 314475 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 9900 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 85548 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 10627 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 58910 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 131027 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 189937 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 54736921 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 10438101 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 258564 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 59687 # number of nop insts executed
system.cpu1.iew.exec_refs 17373742 # number of memory reference insts executed
system.cpu1.iew.exec_branches 11974777 # Number of branches executed
system.cpu1.iew.exec_stores 6935641 # Number of stores executed
system.cpu1.iew.exec_rate 0.514654 # Inst execution rate
system.cpu1.iew.wb_sent 54589285 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 53010114 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 25746768 # num instructions producing a value
system.cpu1.iew.wb_consumers 39490922 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 0.498418 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.651967 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 3744166 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 557673 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 178057 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 103735818 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.501583 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.163784 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 77652029 74.86% 74.86% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 14577800 14.05% 88.91% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 6160967 5.94% 94.85% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 757264 0.73% 95.58% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 2015553 1.94% 97.52% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 1576437 1.52% 99.04% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 460071 0.44% 99.48% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 129756 0.13% 99.61% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 405941 0.39% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 103735818 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 42197750 # Number of instructions committed
system.cpu1.commit.committedOps 52032169 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 16915231 # Number of memory references committed
system.cpu1.commit.loads 10113062 # Number of loads committed
system.cpu1.commit.membars 214317 # Number of memory barriers committed
system.cpu1.commit.branches 11798243 # Number of branches committed
system.cpu1.commit.fp_insts 1928 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 46741115 # Number of committed integer instructions.
system.cpu1.commit.function_calls 3380053 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 35068266 67.40% 67.40% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 45339 0.09% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.48% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 3333 0.01% 67.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.49% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.49% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 10113062 19.44% 86.93% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 6802169 13.07% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 52032169 # Class of committed instruction
system.cpu1.commit.bw_lim_events 405941 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 139039973 # The number of ROB reads
system.cpu1.rob.rob_writes 113498046 # The number of ROB writes
system.cpu1.timesIdled 59982 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 671936 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 5543606797 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 42158419 # Number of Instructions Simulated
system.cpu1.committedOps 51992838 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 2.522787 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 2.522787 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.396387 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.396387 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 57596911 # number of integer regfile reads
system.cpu1.int_regfile_writes 36337307 # number of integer regfile writes
system.cpu1.fp_regfile_reads 1495 # number of floating regfile reads
system.cpu1.fp_regfile_writes 580 # number of floating regfile writes
system.cpu1.cc_regfile_reads 194912842 # number of cc regfile reads
system.cpu1.cc_regfile_writes 16071052 # number of cc regfile writes
system.cpu1.misc_regfile_reads 208513912 # number of misc regfile reads
system.cpu1.misc_regfile_writes 404751 # number of misc regfile writes
system.cpu1.dcache.tags.replacements 201045 # number of replacements
system.cpu1.dcache.tags.tagsinuse 470.607708 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 16083620 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 201364 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 79.873364 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 93308892000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.607708 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.919156 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.919156 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 304 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.623047 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 33778764 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 33778764 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 9715738 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 9715738 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 6106545 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 6106545 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50809 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 50809 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81509 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 81509 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73252 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 73252 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 15822283 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 15822283 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 15873092 # number of overall hits
system.cpu1.dcache.overall_hits::total 15873092 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 224637 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 224637 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 441375 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 441375 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 31038 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 31038 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18294 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 18294 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23669 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 23669 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 666012 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 666012 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 697050 # number of overall misses
system.cpu1.dcache.overall_misses::total 697050 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3524459329 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 3524459329 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10055246312 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 10055246312 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 359810249 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 359810249 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545166265 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 545166265 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 431000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 431000 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 13579705641 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 13579705641 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 13579705641 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 13579705641 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 9940375 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 9940375 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 6547920 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 6547920 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81847 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 81847 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 99803 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 99803 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 96921 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 96921 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 16488295 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 16488295 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 16570142 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 16570142 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022598 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.022598 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.067407 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.067407 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379220 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379220 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.183301 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.183301 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.244209 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.244209 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040393 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.040393 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.042067 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.042067 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15689.576201 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15689.576201 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22781.639903 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 22781.639903 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19668.210834 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19668.210834 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23032.923444 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23032.923444 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20389.581030 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 20389.581030 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19481.680856 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 19481.680856 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 1443381 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 46 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 45166 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.391304 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 31.957247 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 125175 # number of writebacks
system.cpu1.dcache.writebacks::total 125175 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 81304 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 81304 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 345063 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 345063 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13214 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13214 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 426367 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 426367 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 426367 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 426367 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143333 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 143333 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 96312 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 96312 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29478 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 29478 # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5080 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5080 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23669 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 23669 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 239645 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 239645 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 269123 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 269123 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1836231651 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1836231651 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2306828153 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2306828153 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 473894752 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 473894752 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 85053999 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85053999 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 496613735 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 496613735 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 413000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 413000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4143059804 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4143059804 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4616954556 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 4616954556 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298741750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298741750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826982999 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826982999 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125724749 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125724749 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014419 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014419 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014709 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014709 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360160 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360160 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050900 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050900 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.244209 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.244209 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014534 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.014534 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016241 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.016241 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12810.948288 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12810.948288 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23951.617171 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23951.617171 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16076.217925 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16076.217925 # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16742.913189 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16742.913189 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20981.610334 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20981.610334 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17288.321492 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17288.321492 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17155.555475 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17155.555475 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 614958 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.494107 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 43363824 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 615470 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 70.456438 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 78768329500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.494107 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975574 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.975574 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 493 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 88611673 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 88611673 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 43363824 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 43363824 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 43363824 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 43363824 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 43363824 # number of overall hits
system.cpu1.icache.overall_hits::total 43363824 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 634277 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 634277 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 634277 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 634277 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 634277 # number of overall misses
system.cpu1.icache.overall_misses::total 634277 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5597748699 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 5597748699 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 5597748699 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 5597748699 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 5597748699 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 5597748699 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 43998101 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 43998101 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 43998101 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 43998101 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 43998101 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 43998101 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014416 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.014416 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014416 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.014416 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014416 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.014416 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8825.400730 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 8825.400730 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8825.400730 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 8825.400730 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8825.400730 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 8825.400730 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 423261 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 12 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 39865 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 10.617359 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets 12 # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 18806 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 18806 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 18806 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 18806 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 18806 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 18806 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615471 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 615471 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 615471 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 615471 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 615471 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 615471 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4523939883 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 4523939883 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4523939883 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 4523939883 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4523939883 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 4523939883 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8397000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8397000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8397000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 8397000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013989 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013989 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013989 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.013989 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013989 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.013989 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7350.370502 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7350.370502 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7350.370502 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 7350.370502 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7350.370502 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 7350.370502 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued 229039 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 229849 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 714 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 59807 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 55576 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 15296.446244 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 851759 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 70922 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 12.009799 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 8246.965221 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 13.312576 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 3.835357 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3924.928701 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2437.613409 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 669.790981 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.503355 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000813 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000234 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.239559 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.148780 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.040881 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.933621 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 766 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14561 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 18 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 628 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 120 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 646 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 10959 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2956 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.046753 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.888733 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 17259149 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 17259149 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17267 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7675 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.inst 597307 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.data 107002 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 729251 # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks 125175 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 125175 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1610 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 1610 # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1001 # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total 1001 # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 32136 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 32136 # number of ReadExReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17267 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7675 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 597307 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 139138 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 761387 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17267 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7675 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 597307 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 139138 # number of overall hits
system.cpu1.l2cache.overall_hits::total 761387 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 431 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 284 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.inst 18163 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.data 70870 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 89748 # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28235 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 28235 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22667 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 22667 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35014 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 35014 # number of ReadExReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 431 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 284 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 18163 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 105884 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 124762 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 431 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 284 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 18163 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 105884 # number of overall misses
system.cpu1.l2cache.overall_misses::total 124762 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8966500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5677500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 626896483 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1561730924 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 2203271407 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 530022874 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 530022874 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 442433542 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 442433542 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 404000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 404000 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1382751233 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 1382751233 # number of ReadExReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8966500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5677500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 626896483 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 2944482157 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 3586022640 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8966500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5677500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 626896483 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 2944482157 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 3586022640 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17698 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7959 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 615470 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.data 177872 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 818999 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 125175 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 125175 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29845 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 29845 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23668 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 23668 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 67150 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 67150 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17698 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7959 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 615470 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 245022 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 886149 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17698 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7959 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 615470 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 245022 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 886149 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.024353 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.035683 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.029511 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.398433 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.109583 # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.946055 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.946055 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.957707 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.957707 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.521430 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.521430 # miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.024353 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.035683 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.029511 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.432141 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.140791 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.024353 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.035683 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.029511 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.432141 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.140791 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20803.944316 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19991.197183 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34515.029621 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22036.558826 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24549.532101 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18771.838994 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18771.838994 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19518.839811 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19518.839811 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 404000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 404000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39491.381533 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39491.381533 # average ReadExReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20803.944316 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19991.197183 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34515.029621 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27808.565572 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 28742.907616 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20803.944316 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19991.197183 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34515.029621 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27808.565572 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 28742.907616 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 213 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 9 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 23.666667 # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks 33017 # number of writebacks
system.cpu1.l2cache.writebacks::total 33017 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 13 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 83 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 925 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 925 # number of ReadExReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 13 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1008 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 1028 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 13 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1008 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 1028 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 430 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 271 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 18157 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70787 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 89645 # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 28351 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 28351 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28235 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28235 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22667 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22667 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34089 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 34089 # number of ReadExReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 430 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 271 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 18157 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104876 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 123734 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 430 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 271 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 18157 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104876 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 28351 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 152085 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5933500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3621000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 498710017 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1063464434 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1571728951 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1791435833 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1791435833 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 410729057 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 410729057 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 308678233 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308678233 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 341000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 341000 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1031751458 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1031751458 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5933500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3621000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 498710017 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2095215892 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 2603480409 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5933500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3621000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 498710017 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2095215892 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1791435833 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 4394916242 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7547000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2182265750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189812750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737917999 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737917999 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7547000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3920183749 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3927730749 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024297 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034050 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.029501 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.397966 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.109457 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.946055 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.946055 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.957707 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.957707 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.507655 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.507655 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024297 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034050 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.029501 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.428027 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139631 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024297 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034050 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.029501 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.428027 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.171625 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27466.542766 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15023.442638 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17532.812215 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63187.747628 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 63187.747628 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14546.805631 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14546.805631 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13617.957074 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13617.957074 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 341000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 341000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30266.404353 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30266.404353 # average ReadExReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27466.542766 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19978.030169 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21040.945973 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27466.542766 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19978.030169 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63187.747628 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28897.762712 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq 1181364 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 879041 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 11863 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 11863 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback 125175 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 39550 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 75362 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41966 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 86419 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 89279 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 71717 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1231143 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 850974 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17917 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 40354 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 2140388 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 39391696 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 26549567 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 31836 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70792 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 66043891 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 585425 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 1574316 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 5.319194 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.466164 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::5 1071804 68.08% 68.08% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::6 502512 31.92% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 1574316 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 680504524 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 81017999 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 924938756 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 418581676 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 10092231 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 22735342 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 31021 # Transaction distribution
system.iobus.trans_dist::ReadResp 31021 # Transaction distribution
system.iobus.trans_dist::WriteReq 59439 # Transaction distribution
system.iobus.trans_dist::WriteResp 23215 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56654 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 107968 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 180920 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71598 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 162848 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484096 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 40134000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 347085145 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 84753000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36840554 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36458 # number of replacements
system.iocache.tags.tagsinuse 14.558041 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 254609644000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.558041 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.909878 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.909878 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
system.iocache.tags.data_accesses 328284 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 252 # number of overall misses
system.iocache.overall_misses::total 252 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 31425377 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 31425377 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9633411214 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 9633411214 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ide 31425377 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 31425377 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 31425377 # number of overall miss cycles
system.iocache.overall_miss_latency::total 31425377 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 124703.876984 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 124703.876984 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265940.018054 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 265940.018054 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 124703.876984 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 124703.876984 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 124703.876984 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 124703.876984 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 56535 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 7211 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 7.840105 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 36206 # number of writebacks
system.iocache.writebacks::total 36206 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 18320377 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 18320377 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7749655322 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7749655322 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 18320377 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 18320377 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 18320377 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 18320377 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72699.908730 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 72699.908730 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213937.039587 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213937.039587 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 72699.908730 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 72699.908730 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 72699.908730 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 72699.908730 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 131156 # number of replacements
system.l2c.tags.tagsinuse 63989.320892 # Cycle average of tags in use
system.l2c.tags.total_refs 352673 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 195503 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 1.803926 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 11841.549695 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.064672 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 2.035376 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 7520.794001 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2869.625937 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37329.338161 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.624339 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909611 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1925.336025 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 701.530072 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1779.513002 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.180688 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000215 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000031 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.114758 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.043787 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.569600 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000071 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.029378 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.010704 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027153 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.976400 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 31812 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 32516 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 220 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 6391 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 25201 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 410 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 6149 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 25933 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.485413 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.496155 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 5013444 # Number of tag accesses
system.l2c.tags.data_accesses 5013444 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 174 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 66 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 34010 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 46649 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45581 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 75 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 50 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 15163 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 9968 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 4879 # number of ReadReq hits
system.l2c.ReadReq_hits::total 156615 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 227099 # number of Writeback hits
system.l2c.Writeback_hits::total 227099 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 2891 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 673 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 3564 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 168 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 175 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 343 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 3845 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 1635 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 5480 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 174 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 66 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 34010 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 50494 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 45581 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 75 # number of demand (read+write) hits
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system.l2c.UpgradeReq_mshr_misses::total 11546 # number of UpgradeReq MSHR misses
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system.l2c.ReadReq_mshr_miss_latency::total 16172119054 # number of ReadReq MSHR miss cycles
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system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 29737438 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 116409977 # number of UpgradeReq MSHR miss cycles
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system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12430724 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 19270873 # number of SCUpgradeReq MSHR miss cycles
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system.l2c.demand_mshr_miss_latency::total 17539408393 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2044750 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 340000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles
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system.l2c.overall_mshr_miss_latency::total 17539408393 # number of overall MSHR miss cycles
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system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3685006498 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5557500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1920304250 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 5769713248 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2711627000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1536025000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 4247652000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 158845000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6396633498 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5557500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3456329250 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 10017365248 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.125628 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.043478 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.364321 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.163664 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737915 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.164519 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.115842 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.686983 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.523384 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.748237 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.814447 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.764130 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.799762 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.876062 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.847623 # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.744212 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.835463 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.780528 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.125628 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.043478 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.364321 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.286905 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737915 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.164519 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.452973 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.686983 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.541543 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.125628 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.043478 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.364321 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.286905 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737915 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.164519 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.452973 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.686983 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.541543 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 81790 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 67083.333333 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62600.073514 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 72210.099135 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97183.721832 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65789.670907 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73214.777182 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142482.158666 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 94027.774700 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10087.586010 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10066.837508 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10082.277585 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10193.962742 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10049.089733 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10100.038260 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75462.216144 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63008.133823 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 70156.977731 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81790 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67083.333333 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62600.073514 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74000.876501 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97183.721832 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65789.670907 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64395.506453 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142482.158666 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 91598.209717 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81790 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67083.333333 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62600.073514 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74000.876501 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97183.721832 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65789.670907 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64395.506453 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142482.158666 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 91598.209717 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 210212 # Transaction distribution
system.membus.trans_dist::ReadResp 210211 # Transaction distribution
system.membus.trans_dist::WriteReq 30942 # Transaction distribution
system.membus.trans_dist::WriteResp 30942 # Transaction distribution
system.membus.trans_dist::Writeback 135769 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.membus.trans_dist::UpgradeReq 76140 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 40614 # Transaction distribution
system.membus.trans_dist::UpgradeResp 13546 # Transaction distribution
system.membus.trans_dist::ReadExReq 39344 # Transaction distribution
system.membus.trans_dist::ReadExResp 19397 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107968 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13598 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 648466 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 770072 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 878993 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162848 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27196 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18669148 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 18859512 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 23495992 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 123727 # Total snoops (count)
system.membus.snoop_fanout::samples 500337 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 500337 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 500337 # Request fanout histogram
system.membus.reqLayer0.occupancy 81279500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 26000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 11516000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 1822464250 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 1904793274 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
system.membus.respLayer3.occupancy 38546446 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.trans_dist::ReadReq 489006 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 488990 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 30942 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 30942 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 227099 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 79612 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 40957 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 120569 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 20 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 50358 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 50358 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1016462 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 341372 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1357834 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31696041 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5742799 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 37438840 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 287500 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 885309 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.041201 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.198756 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 848833 95.88% 95.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 36476 4.12% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 885309 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 1431615961 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 1066500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 1714942226 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 674969400 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 1858 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2745 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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