gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
Andreas Hansson c4e91289ae stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
2014-09-20 17:18:53 -04:00

215 lines
23 KiB
Text

---------- Begin Simulation Statistics ----------
sim_seconds 0.832017 # Number of seconds simulated
sim_ticks 832017490000 # Number of ticks simulated
final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 2048371 # Simulator instruction rate (inst/s)
host_op_rate 2206809 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 1103406177 # Simulator tick rate (ticks/s)
host_mem_usage 296712 # Number of bytes of host memory used
host_seconds 754.04 # Real time elapsed on the host
sim_insts 1544563041 # Number of instructions simulated
sim_ops 1664032433 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory
system.physmem.bytes_read::total 7759650027 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 6178262356 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 6178262356 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory
system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1544565589 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1999474786 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory
system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1900666380 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 9326306382 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2650840985 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10076480987 # Total bandwidth to/from this memory (bytes/s)
system.membus.trans_dist::ReadReq 1999474724 # Transaction distribution
system.membus.trans_dist::ReadResp 1999474785 # Transaction distribution
system.membus.trans_dist::WriteReq 172586047 # Transaction distribution
system.membus.trans_dist::WriteResp 172586047 # Transaction distribution
system.membus.trans_dist::SoftPFReq 1 # Transaction distribution
system.membus.trans_dist::SoftPFResp 1 # Transaction distribution
system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution
system.membus.trans_dist::StoreCondReq 61 # Transaction distribution
system.membus.trans_dist::StoreCondResp 61 # Transaction distribution
system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131178 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4344121788 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262356 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram
system.membus.snoop_fanout::mean 4.711106 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::4 627495305 28.89% 28.89% # Request fanout histogram
system.membus.snoop_fanout::5 1544565589 71.11% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 4 # Request fanout histogram
system.membus.snoop_fanout::max_value 5 # Request fanout histogram
system.membus.snoop_fanout::total 2172060894 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 1664034981 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1544563041 # Number of instructions committed
system.cpu.committedOps 1664032433 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
system.cpu.num_func_calls 27330256 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls
system.cpu.num_int_insts 1477900422 # number of integer instructions
system.cpu.num_fp_insts 36 # number of float instructions
system.cpu.num_int_register_reads 2605402942 # number of times the integer registers were read
system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
system.cpu.num_cc_register_reads 4992096236 # number of times the CC registers were read
system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
system.cpu.num_mem_refs 633153380 # number of memory refs
system.cpu.num_load_insts 458306334 # Number of load instructions
system.cpu.num_store_insts 174847046 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 1664034981 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 213462426 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction
system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction
system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction
system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1664032480 # Class of executed instruction
---------- End Simulation Statistics ----------