c4e91289ae
This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
1153 lines
132 KiB
Text
1153 lines
132 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.753004 # Number of seconds simulated
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sim_ticks 753003557500 # Number of ticks simulated
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final_tick 753003557500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 139511 # Simulator instruction rate (inst/s)
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host_op_rate 150302 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 68014357 # Simulator tick rate (ticks/s)
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host_mem_usage 308752 # Number of bytes of host memory used
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host_seconds 11071.24 # Real time elapsed on the host
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sim_insts 1544563023 # Number of instructions simulated
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sim_ops 1664032415 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 14592 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 231381248 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.l2cache.prefetcher 95077696 # Number of bytes read from this memory
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system.physmem.bytes_read::total 326473536 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 14592 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 14592 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 107048704 # Number of bytes written to this memory
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system.physmem.bytes_written::total 107048704 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 228 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 3615332 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.l2cache.prefetcher 1485589 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 5101149 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 1672636 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 1672636 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 19378 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 307277762 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.l2cache.prefetcher 126264604 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 433561744 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 19378 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 19378 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 142162282 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 142162282 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 142162282 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 19378 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 307277762 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.l2cache.prefetcher 126264604 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 575724026 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 5101149 # Number of read requests accepted
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system.physmem.writeReqs 1672636 # Number of write requests accepted
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system.physmem.readBursts 5101149 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 1672636 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 326003456 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 470080 # Total number of bytes read from write queue
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system.physmem.bytesWritten 107046272 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 326473536 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 107048704 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 7345 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 320458 # Per bank write bursts
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system.physmem.perBankRdBursts::1 318552 # Per bank write bursts
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system.physmem.perBankRdBursts::2 312159 # Per bank write bursts
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system.physmem.perBankRdBursts::3 320321 # Per bank write bursts
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system.physmem.perBankRdBursts::4 313091 # Per bank write bursts
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system.physmem.perBankRdBursts::5 313451 # Per bank write bursts
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system.physmem.perBankRdBursts::6 306429 # Per bank write bursts
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system.physmem.perBankRdBursts::7 300886 # Per bank write bursts
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system.physmem.perBankRdBursts::8 320656 # Per bank write bursts
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system.physmem.perBankRdBursts::9 326914 # Per bank write bursts
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system.physmem.perBankRdBursts::10 318873 # Per bank write bursts
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system.physmem.perBankRdBursts::11 328947 # Per bank write bursts
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system.physmem.perBankRdBursts::12 326980 # Per bank write bursts
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system.physmem.perBankRdBursts::13 328236 # Per bank write bursts
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system.physmem.perBankRdBursts::14 322345 # Per bank write bursts
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system.physmem.perBankRdBursts::15 315506 # Per bank write bursts
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system.physmem.perBankWrBursts::0 106372 # Per bank write bursts
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system.physmem.perBankWrBursts::1 103970 # Per bank write bursts
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system.physmem.perBankWrBursts::2 101390 # Per bank write bursts
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system.physmem.perBankWrBursts::3 102163 # Per bank write bursts
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system.physmem.perBankWrBursts::4 101308 # Per bank write bursts
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system.physmem.perBankWrBursts::5 100856 # Per bank write bursts
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system.physmem.perBankWrBursts::6 104858 # Per bank write bursts
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system.physmem.perBankWrBursts::7 106447 # Per bank write bursts
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system.physmem.perBankWrBursts::8 107624 # Per bank write bursts
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system.physmem.perBankWrBursts::9 106732 # Per bank write bursts
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system.physmem.perBankWrBursts::10 104273 # Per bank write bursts
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system.physmem.perBankWrBursts::11 105282 # Per bank write bursts
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system.physmem.perBankWrBursts::12 105198 # Per bank write bursts
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system.physmem.perBankWrBursts::13 104874 # Per bank write bursts
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system.physmem.perBankWrBursts::14 106564 # Per bank write bursts
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system.physmem.perBankWrBursts::15 104687 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 753003515500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 5101149 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 1672636 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 2761902 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 1096580 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 406963 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 307813 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 214927 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 130899 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 69362 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 43944 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 31968 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 12494 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 6876 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 4504 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 2574 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1592 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 933 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 473 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 23634 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 25442 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 58935 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 74795 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 85216 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 93468 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 100234 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 105264 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 108420 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 110279 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 111519 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 112924 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 114921 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 116959 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 109523 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 106852 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 104984 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 103460 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 3249 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 1379 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 606 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 281 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 133 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 39 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 11 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 2 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 4344411 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 99.679291 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 80.657847 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 113.406930 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 3407328 78.43% 78.43% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 696147 16.02% 94.45% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 107309 2.47% 96.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 43326 1.00% 97.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 33261 0.77% 98.69% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 16273 0.37% 99.06% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 9699 0.22% 99.28% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 6677 0.15% 99.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 24391 0.56% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 4344411 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 100519 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 50.674768 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::gmean 34.618065 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 99.194987 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-255 98006 97.50% 97.50% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::256-511 1235 1.23% 98.73% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::512-767 738 0.73% 99.46% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::768-1023 394 0.39% 99.85% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::1024-1279 104 0.10% 99.96% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::1280-1535 26 0.03% 99.98% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::1536-1791 7 0.01% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::2304-2559 2 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::3072-3327 2 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 100519 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 100519 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::mean 16.639620 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.599991 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 1.204272 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16 73763 73.38% 73.38% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::17 1810 1.80% 75.18% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::18 17937 17.84% 93.03% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::19 4183 4.16% 97.19% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20 1485 1.48% 98.67% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::21 646 0.64% 99.31% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::22 326 0.32% 99.63% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::23 183 0.18% 99.81% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24 100 0.10% 99.91% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::25 51 0.05% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::26 16 0.02% 99.98% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::27 9 0.01% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28 2 0.00% 99.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::29 3 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::30 3 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 100519 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 147032532073 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 242541357073 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 25469020000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 28864.98 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 47614.98 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 432.94 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 142.16 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 433.56 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 142.16 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 4.49 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 3.38 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 1.11 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 2056015 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 365966 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 40.36 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 21.88 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 111164.37 # Average gap between requests
|
|
system.physmem.pageHitRate 35.79 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 77100737509 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 25144340000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 650755672741 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.membus.trans_dist::ReadReq 4164250 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 4164249 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 1672636 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 936899 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 936899 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11874933 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 11874933 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 433522176 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 433522176 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 6773785 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 6773785 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 6773785 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 21336071694 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 47387677526 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 6.3 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.branchPred.lookups 286237274 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 223376247 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 14631258 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 157873028 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 150326972 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 95.220174 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 16640209 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions.
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 46 # Number of system calls
|
|
system.cpu.numCycles 1506007116 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 13915908 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 2067206547 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 286237274 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 166967181 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 1477423210 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 29286858 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 656844028 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 587 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 1505982817 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 1.470565 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 1.223309 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 423738570 28.14% 28.14% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 465347942 30.90% 59.04% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 101390896 6.73% 65.77% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 515505409 34.23% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 1505982817 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.190064 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.372641 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 74738188 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 508470466 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 849951241 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 58180203 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 14642719 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 42195522 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 748 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 2037029518 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 52402529 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 14642719 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 139800206 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 434773312 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 14137 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 837909741 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 78842702 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 1976226014 # Number of instructions processed by rename
|
|
system.cpu.rename.SquashedInsts 26698193 # Number of squashed instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 45123172 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 125355 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 1314299 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 18015097 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 1985707207 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 9127389229 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 2432660668 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 146 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 310808262 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 156 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 144 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 111604908 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 542499825 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 199292304 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 26858708 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 28865215 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 1947820848 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 1857727691 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 13537484 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 279225798 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 646033301 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 1505982817 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 1.233565 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.149736 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 553461726 36.75% 36.75% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 325286672 21.60% 58.35% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 378400557 25.13% 83.48% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 219701727 14.59% 98.07% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 29125951 1.93% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 6184 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 1505982817 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 166582994 41.01% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 1992 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.01% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 191579576 47.17% 88.18% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 48024706 11.82% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 1138365513 61.28% 61.28% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 800977 0.04% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 27 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 26 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 532245079 28.65% 89.97% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 186316069 10.03% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 1857727691 # Type of FU issued
|
|
system.cpu.iq.rate 1.233545 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 406189268 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.218648 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 5641164724 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 2227059400 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 1805827330 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 227 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 234 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 67 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 2263916833 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 126 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 17868715 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 84193491 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 66602 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 12979 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 24445259 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 4569389 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 5015263 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 14642719 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 25280273 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 1153411 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 1947821148 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 542499825 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 199292304 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 152 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 158606 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 993784 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 12979 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 7710323 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 8723960 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 16434283 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 1828067374 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 517076026 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 29660317 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 86 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 698832649 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 229600081 # Number of branches executed
|
|
system.cpu.iew.exec_stores 181756623 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.213850 # Inst execution rate
|
|
system.cpu.iew.wb_sent 1808848691 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 1805827397 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1169333238 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 1689629138 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.199083 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.692065 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 257853927 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 14630548 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 1466512041 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.134687 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.044179 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 886829793 60.47% 60.47% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 250699029 17.09% 77.57% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 109472668 7.46% 85.03% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 55016344 3.75% 88.78% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 29216480 1.99% 90.78% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 33954895 2.32% 93.09% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 24874922 1.70% 94.79% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 18134171 1.24% 96.02% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 58313739 3.98% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 1466512041 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
|
|
system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 633153379 # Number of memory references committed
|
|
system.cpu.commit.loads 458306334 # Number of loads committed
|
|
system.cpu.commit.membars 62 # Number of memory barriers committed
|
|
system.cpu.commit.branches 213462426 # Number of branches committed
|
|
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 1030178729 61.91% 61.91% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 58313739 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 3330084063 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 3883248691 # The number of ROB writes
|
|
system.cpu.timesIdled 433 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 24299 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.975038 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.975038 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.025601 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.025601 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 2176017050 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 1261587528 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 38 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 49 # number of floating regfile writes
|
|
system.cpu.cc_regfile_reads 6966468810 # number of cc regfile reads
|
|
system.cpu.cc_regfile_writes 551975360 # number of cc regfile writes
|
|
system.cpu.misc_regfile_reads 675847678 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 14271352 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 14271352 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 4800041 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::HardPFReq 2156446 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 2737659 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 2737659 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2176 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38815887 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 38818063 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69632 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1395709696 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 1395779328 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 2156446 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 23967212 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 5.089975 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.286146 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::5 21810766 91.00% 91.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::6 2156446 9.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 23967212 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 15706134446 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1655247 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 25977831897 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 600 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 446.759697 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 656842791 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 1088 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 603715.800551 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 446.759697 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.872578 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.872578 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 1313689140 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 1313689140 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 656842791 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 656842791 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 656842791 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 656842791 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 656842791 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 656842791 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 1235 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 1235 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 1235 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 1235 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 1235 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 1235 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 31675742 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 31675742 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 31675742 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 31675742 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 31675742 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 31675742 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 656844026 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 656844026 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 656844026 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 656844026 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 656844026 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 656844026 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25648.374089 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 25648.374089 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 25648.374089 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 25648.374089 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 25648.374089 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 25648.374089 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 3135 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 123 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 25.487805 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 147 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 147 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 147 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 147 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 147 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 147 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1088 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 1088 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 1088 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 1088 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 1088 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 1088 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25912248 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 25912248 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25912248 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 25912248 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25912248 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 25912248 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23816.404412 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23816.404412 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23816.404412 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 23816.404412 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23816.404412 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 23816.404412 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 15355050 # number of hwpf identified
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 500576 # number of hwpf that were already in mshr
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 12135733 # number of hwpf that were already in the cache
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 866797 # number of hwpf that were already in the prefetch queue
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 351771 # number of hwpf removed because MSHR allocated
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 1500173 # number of hwpf issued
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 5090638 # number of hwpf spanning a virtual page
|
|
system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
|
system.cpu.l2cache.tags.replacements 5094046 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 16133.549273 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 15376042 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 5109996 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 3.009013 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 29446587000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 4939.304770 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3.959471 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 6800.251946 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 4390.033086 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.301471 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000242 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.415054 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.267946 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.984714 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1022 1027 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 14923 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 102 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::1 570 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::2 7 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::3 346 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1022::4 2 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 521 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2353 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1208 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9340 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1022 0.062683 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.910828 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 356792487 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 356792487 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 832 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 11525794 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 11526626 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 4800041 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 4800041 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 1796540 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 1796540 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 832 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 13322334 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 13323166 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 832 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 13322334 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 13323166 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 256 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 2744470 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 2744726 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 941119 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 941119 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 256 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 3685589 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 3685845 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 256 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 3685589 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 3685845 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19831249 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 216838606544 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 216858437793 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 93637023447 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 93637023447 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 19831249 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 310475629991 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 310495461240 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 19831249 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 310475629991 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 310495461240 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1088 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 14270264 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 14271352 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 4800041 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 4800041 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737659 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 2737659 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1088 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 17007923 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 17009011 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1088 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 17007923 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 17009011 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.235294 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.192321 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.192324 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.343768 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.343768 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235294 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.216698 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.216700 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235294 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.216698 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.216700 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77465.816406 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79009.282865 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 79009.138906 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 99495.412851 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 99495.412851 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77465.816406 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84240.437550 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 84239.967020 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77465.816406 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84240.437550 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 84239.967020 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 114068 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 3696 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 30.862554 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 1672636 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 1672636 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 28 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 67618 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 67646 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 4482 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.ReadExReq_mshr_hits::total 4482 # number of ReadExReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 72100 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 72128 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 72100 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 72128 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2676852 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 2677080 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1500168 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.HardPFReq_mshr_misses::total 1500168 # number of HardPFReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 936637 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 936637 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 3613489 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 3613717 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 3613489 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1500168 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 5113885 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16681749 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 190526161225 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 190542842974 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 108098150766 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 108098150766 # number of HardPFReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 85432139513 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 85432139513 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16681749 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 275958300738 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 275974982487 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16681749 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 275958300738 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 108098150766 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 384073133253 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.209559 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.187583 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.187584 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.342131 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.342131 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.209559 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.212459 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.212459 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.209559 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.212459 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.300657 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 73165.565789 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71175.455806 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71175.625298 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72057.363419 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 72057.363419 # average HardPFReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91211.578779 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91211.578779 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73165.565789 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76368.933388 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76368.731278 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73165.565789 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76368.933388 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 72057.363419 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75103.983225 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 17007411 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.965023 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 638377840 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 17007923 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 37.534145 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 77012000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.965023 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 449 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 1335546211 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 1335546211 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 469430568 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 469430568 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 168947154 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 168947154 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 638377722 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 638377722 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 638377722 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 638377722 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 17252405 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 17252405 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 3638893 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 3638893 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 20891298 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 20891298 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 20891300 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 20891300 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 389285003128 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 389285003128 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 129453998118 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 129453998118 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 384750 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 384750 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 518739001246 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 518739001246 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 518739001246 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 518739001246 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 486682973 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 486682973 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 659269020 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 659269020 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 659269022 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 659269022 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035449 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.035449 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.021085 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.021085 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.031689 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.031689 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.031689 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.031689 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22564.100665 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 22564.100665 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35575.104329 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 35575.104329 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 96187.500000 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 96187.500000 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 24830.386376 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 24830.386376 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 24830.383999 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 24830.383999 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 20820542 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 1650046 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 1039120 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 52884 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.036706 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 31.201233 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 4800041 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 4800041 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2982110 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 2982110 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 901266 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 901266 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 3883376 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 3883376 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 3883376 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 3883376 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14270295 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 14270295 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737627 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 2737627 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 17007922 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 17007922 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 17007923 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 17007923 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 301459973376 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 301459973376 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 108130443900 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 108130443900 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 101000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 101000 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 409590417276 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 409590417276 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 409590518276 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 409590518276 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029322 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029322 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025798 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.025798 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025798 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.025798 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21124.999404 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21124.999404 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39497.873122 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39497.873122 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 101000 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 101000 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24082.331591 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 24082.331591 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24082.336113 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 24082.336113 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|