c4e91289ae
This patch bumps the stats to reflect the addition of the snoop filter and snoop stats, the change from bus to crossbar, and the updates to the ARM regressions that are now using a different CPU and cache configuration. Lastly, some minor changes are expected due to the activation cleanup of the CPUs.
979 lines
111 KiB
Text
979 lines
111 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.069652 # Number of seconds simulated
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sim_ticks 69651704000 # Number of ticks simulated
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final_tick 69651704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 258321 # Simulator instruction rate (inst/s)
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host_op_rate 258321 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 47906543 # Simulator tick rate (ticks/s)
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host_mem_usage 298148 # Number of bytes of host memory used
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host_seconds 1453.91 # Real time elapsed on the host
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sim_insts 375574808 # Number of instructions simulated
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sim_ops 375574808 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 221568 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 255744 # Number of bytes read from this memory
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system.physmem.bytes_read::total 477312 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 221568 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 221568 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 3462 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 3996 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 7458 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 3181085 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 3671755 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 6852840 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 3181085 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 3181085 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 3181085 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 3671755 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 6852840 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 7458 # Number of read requests accepted
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system.physmem.writeReqs 0 # Number of write requests accepted
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system.physmem.readBursts 7458 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 477312 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
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system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 477312 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 528 # Per bank write bursts
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system.physmem.perBankRdBursts::1 655 # Per bank write bursts
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system.physmem.perBankRdBursts::2 455 # Per bank write bursts
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system.physmem.perBankRdBursts::3 602 # Per bank write bursts
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system.physmem.perBankRdBursts::4 446 # Per bank write bursts
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system.physmem.perBankRdBursts::5 454 # Per bank write bursts
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system.physmem.perBankRdBursts::6 515 # Per bank write bursts
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system.physmem.perBankRdBursts::7 524 # Per bank write bursts
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system.physmem.perBankRdBursts::8 439 # Per bank write bursts
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system.physmem.perBankRdBursts::9 406 # Per bank write bursts
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system.physmem.perBankRdBursts::10 340 # Per bank write bursts
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system.physmem.perBankRdBursts::11 305 # Per bank write bursts
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system.physmem.perBankRdBursts::12 414 # Per bank write bursts
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system.physmem.perBankRdBursts::13 542 # Per bank write bursts
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system.physmem.perBankRdBursts::14 454 # Per bank write bursts
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system.physmem.perBankRdBursts::15 379 # Per bank write bursts
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system.physmem.perBankWrBursts::0 0 # Per bank write bursts
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system.physmem.perBankWrBursts::1 0 # Per bank write bursts
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system.physmem.perBankWrBursts::2 0 # Per bank write bursts
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system.physmem.perBankWrBursts::3 0 # Per bank write bursts
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system.physmem.perBankWrBursts::4 0 # Per bank write bursts
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system.physmem.perBankWrBursts::5 0 # Per bank write bursts
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system.physmem.perBankWrBursts::6 0 # Per bank write bursts
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system.physmem.perBankWrBursts::7 0 # Per bank write bursts
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system.physmem.perBankWrBursts::8 0 # Per bank write bursts
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system.physmem.perBankWrBursts::9 0 # Per bank write bursts
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system.physmem.perBankWrBursts::10 0 # Per bank write bursts
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system.physmem.perBankWrBursts::11 0 # Per bank write bursts
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system.physmem.perBankWrBursts::12 0 # Per bank write bursts
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system.physmem.perBankWrBursts::13 0 # Per bank write bursts
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system.physmem.perBankWrBursts::14 0 # Per bank write bursts
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system.physmem.perBankWrBursts::15 0 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 69651614500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 7458 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 4226 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 1956 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 918 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 63 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 1353 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 350.509978 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 208.823320 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 348.868335 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 424 31.34% 31.34% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 330 24.39% 55.73% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 151 11.16% 66.89% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 84 6.21% 73.10% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 54 3.99% 77.09% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 42 3.10% 80.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 39 2.88% 83.07% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 25 1.85% 84.92% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 204 15.08% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 1353 # Bytes accessed per row activation
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system.physmem.totQLat 66704750 # Total ticks spent queuing
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system.physmem.totMemAccLat 206542250 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 37290000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 8944.05 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 27694.05 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 6.85 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 6.85 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 0.05 # Data bus utilization in percentage
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system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
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system.physmem.readRowHits 6096 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 81.74 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 9339181.35 # Average gap between requests
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system.physmem.pageHitRate 81.74 # Row buffer hit rate, read and write combined
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system.physmem.memoryStateTime::IDLE 66207575500 # Time in different power states
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system.physmem.memoryStateTime::REF 2325700000 # Time in different power states
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system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
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system.physmem.memoryStateTime::ACT 1115004500 # Time in different power states
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system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
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system.membus.trans_dist::ReadReq 4328 # Transaction distribution
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system.membus.trans_dist::ReadResp 4328 # Transaction distribution
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system.membus.trans_dist::ReadExReq 3130 # Transaction distribution
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system.membus.trans_dist::ReadExResp 3130 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes)
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system.membus.snoops 0 # Total snoops (count)
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system.membus.snoop_fanout::samples 7458 # Request fanout histogram
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system.membus.snoop_fanout::mean 0 # Request fanout histogram
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system.membus.snoop_fanout::stdev 0 # Request fanout histogram
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system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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system.membus.snoop_fanout::0 7458 100.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::min_value 0 # Request fanout histogram
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system.membus.snoop_fanout::max_value 0 # Request fanout histogram
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system.membus.snoop_fanout::total 7458 # Request fanout histogram
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system.membus.reqLayer0.occupancy 9424000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.respLayer1.occupancy 69710500 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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system.cpu.branchPred.lookups 51167476 # Number of BP lookups
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system.cpu.branchPred.condPredicted 29641015 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 1213095 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 25804997 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 23600999 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 91.459026 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 9351095 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 307 # Number of incorrect RAS predictions.
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 103696201 # DTB read hits
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system.cpu.dtb.read_misses 91462 # DTB read misses
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system.cpu.dtb.read_acv 49407 # DTB read access violations
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system.cpu.dtb.read_accesses 103787663 # DTB read accesses
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system.cpu.dtb.write_hits 79414480 # DTB write hits
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system.cpu.dtb.write_misses 1579 # DTB write misses
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system.cpu.dtb.write_acv 2 # DTB write access violations
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system.cpu.dtb.write_accesses 79416059 # DTB write accesses
|
|
system.cpu.dtb.data_hits 183110681 # DTB hits
|
|
system.cpu.dtb.data_misses 93041 # DTB misses
|
|
system.cpu.dtb.data_acv 49409 # DTB access violations
|
|
system.cpu.dtb.data_accesses 183203722 # DTB accesses
|
|
system.cpu.itb.fetch_hits 51277823 # ITB hits
|
|
system.cpu.itb.fetch_misses 422 # ITB misses
|
|
system.cpu.itb.fetch_acv 0 # ITB acv
|
|
system.cpu.itb.fetch_accesses 51278245 # ITB accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.read_acv 0 # DTB read access violations
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.write_acv 0 # DTB write access violations
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.data_hits 0 # DTB hits
|
|
system.cpu.itb.data_misses 0 # DTB misses
|
|
system.cpu.itb.data_acv 0 # DTB access violations
|
|
system.cpu.itb.data_accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 215 # Number of system calls
|
|
system.cpu.numCycles 139303411 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 52063861 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 457094552 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 51167476 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 32952094 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 85692225 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 2532764 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 13783 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR
|
|
system.cpu.fetch.CacheLines 51277823 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 545280 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 139036455 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 3.287588 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 3.344928 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 58307210 41.94% 41.94% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 4519217 3.25% 45.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 7280822 5.24% 50.42% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 5545601 3.99% 54.41% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 11970287 8.61% 63.02% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 8019991 5.77% 68.79% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 5933035 4.27% 73.06% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 1884761 1.36% 74.41% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 35575531 25.59% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 139036455 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.367310 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 3.281288 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 45112319 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 16348091 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 71786999 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 4526862 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 1262184 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 9563244 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 4245 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 451283163 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 14200 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 1262184 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 47010962 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 5663544 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 518995 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 74309214 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 10271556 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 447721649 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 439815 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 2540100 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LQFullEvents 2926498 # Number of times rename has blocked due to LQ full
|
|
system.cpu.rename.SQFullEvents 3600572 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 292278306 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 589607782 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 419965282 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 169642499 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 32745977 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 37893 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 316 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 16173803 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 106306370 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 81667386 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 12470725 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 9729569 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 414594685 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 306 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 406915916 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 484036 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 38878487 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 18208108 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 139036455 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 2.926685 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 2.221928 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 23891375 17.18% 17.18% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 19616672 14.11% 31.29% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 22677489 16.31% 47.60% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 18900240 13.59% 61.20% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 19609416 14.10% 75.30% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 14153870 10.18% 85.48% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 9626407 6.92% 92.40% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 6209798 4.47% 96.87% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 4351188 3.13% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 139036455 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 258477 1.29% 1.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 145250 0.73% 2.02% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 90218 0.45% 2.47% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 2947 0.01% 2.49% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 3497968 17.50% 19.99% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 1676632 8.39% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.38% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 9338598 46.73% 75.10% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 4976149 24.90% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 153207489 37.65% 37.66% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 2128182 0.52% 38.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.18% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 37392506 9.19% 47.37% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 7524499 1.85% 49.22% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 2804822 0.69% 49.91% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 16757586 4.12% 54.03% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 1601657 0.39% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.42% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 105367867 25.89% 80.32% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 80097727 19.68% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 406915916 # Type of FU issued
|
|
system.cpu.iq.rate 2.921076 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 19986240 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.049116 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 625896924 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 265989715 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 237228630 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 347441639 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 187559752 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 163339265 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 246150912 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 180717663 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 19936358 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 11551883 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 163597 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 76334 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 8146657 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 381699 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 4486 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 1262184 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 4471526 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 139226 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 439574480 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 145285 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 106306370 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 81667386 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 306 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 6690 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 131709 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 76334 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 976027 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 412585 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1388612 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 403157734 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 103837101 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 3758182 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 24979489 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 183253197 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 46959988 # Number of branches executed
|
|
system.cpu.iew.exec_stores 79416096 # Number of stores executed
|
|
system.cpu.iew.exec_rate 2.894098 # Inst execution rate
|
|
system.cpu.iew.wb_sent 401401506 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 400567895 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 198000445 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 283955599 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 2.875507 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.697294 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 40912072 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 1208897 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 133310602 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.990494 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 3.213946 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 48555591 36.42% 36.42% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 18055922 13.54% 49.97% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 9630864 7.22% 57.19% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 8737321 6.55% 63.75% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 6426217 4.82% 68.57% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 4404757 3.30% 71.87% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 4988495 3.74% 75.61% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 2616133 1.96% 77.57% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 29895302 22.43% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 133310602 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 398664583 # Number of instructions committed
|
|
system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 168275216 # Number of memory references committed
|
|
system.cpu.commit.loads 94754487 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 44587533 # Number of branches committed
|
|
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 316365839 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 141652545 35.53% 41.33% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 94754487 23.77% 81.56% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 29895302 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 542988978 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 884890973 # The number of ROB writes
|
|
system.cpu.timesIdled 3472 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 266956 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 375574808 # Number of Instructions Simulated
|
|
system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 0.370907 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.370907 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 2.696092 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 2.696092 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 403240144 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 171897287 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 157938395 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 105579710 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 3203 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 3203 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 8966 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 8966 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 8966 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 6787000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 6700000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 2164 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1832.364308 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 51272145 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 4091 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 12532.912491 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364308 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.894709 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.894709 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1343 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 102559737 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 102559737 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 51272145 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 51272145 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 51272145 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 51272145 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 51272145 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 51272145 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 5678 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 5678 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 5678 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 5678 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 5678 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 5678 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 340036249 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 340036249 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 340036249 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 340036249 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 340036249 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 340036249 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 51277823 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 51277823 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 51277823 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 51277823 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 51277823 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 51277823 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000111 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000111 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000111 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000111 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000111 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000111 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59886.623635 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 59886.623635 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 59886.623635 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 59886.623635 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 59886.623635 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 59886.623635 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 58.666667 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1587 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 1587 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 1587 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 1587 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 1587 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 1587 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4091 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 4091 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 4091 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 4091 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 4091 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 4091 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249962500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 249962500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249962500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 249962500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249962500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 249962500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61100.586654 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61100.586654 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61100.586654 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 61100.586654 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61100.586654 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 61100.586654 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 4021.632026 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 866 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 4864 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.178043 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 371.133812 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2983.662944 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 666.835269 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.011326 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.091054 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.020350 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.122730 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4864 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4046 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148438 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 79795 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 79795 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 629 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 132 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 761 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 674 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 674 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 73 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 73 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 629 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 205 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 834 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 629 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 205 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 834 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3462 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 866 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 4328 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 3130 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 3130 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3462 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 3996 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 7458 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3462 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 3996 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 7458 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239571000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65252750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 304823750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 231908750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 231908750 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 239571000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 297161500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 536732500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 239571000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 297161500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 536732500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 998 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 5089 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 674 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 674 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 3203 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 3203 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 4091 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 4201 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 8292 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 4091 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 4201 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 8292 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.846248 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.867735 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.850462 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.977209 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.977209 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.846248 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.951202 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.899421 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.846248 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.951202 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.899421 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69200.173310 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75349.595843 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70430.626155 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74092.252396 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74092.252396 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69200.173310 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74364.739740 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 71967.350496 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69200.173310 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74364.739740 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 71967.350496 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3462 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 866 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 4328 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3462 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 3996 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 7458 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 3996 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 7458 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195687500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54580750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250268250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193330750 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193330750 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195687500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 247911500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 443599000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195687500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 247911500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 443599000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867735 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850462 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.977209 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.977209 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.899421 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.899421 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56524.407857 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63026.270208 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57825.381238 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61767.012780 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61767.012780 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56524.407857 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62039.914915 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59479.619201 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56524.407857 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62039.914915 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59479.619201 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 798 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 3297.113011 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 156873476 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 4201 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 37341.936682 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113011 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.804959 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.804959 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 313794583 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 313794583 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 83372633 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 83372633 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 73500836 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 73500836 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 156873469 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 156873469 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 156873469 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 156873469 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1822 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1822 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 19893 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 19893 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 21715 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 21715 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 21715 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 21715 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 114579750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 114579750 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125182835 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 1125182835 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 1239762585 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 1239762585 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 1239762585 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 1239762585 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 83374455 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 83374455 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 156895184 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 156895184 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 156895184 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 156895184 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62886.800220 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 62886.800220 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56561.747097 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 56561.747097 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 57092.451531 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 57092.451531 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 57092.451531 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 57092.451531 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 46428 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 947 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.026399 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 674 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 674 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16690 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 16690 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 17514 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 17514 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 17514 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 17514 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3203 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 3203 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 4201 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67663750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 67663750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235941750 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 235941750 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303605500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 303605500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303605500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 303605500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67799.348697 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67799.348697 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73662.738058 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73662.738058 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72269.816710 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 72269.816710 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72269.816710 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 72269.816710 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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|
|
|
---------- End Simulation Statistics ----------
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