716ceb6c10
arch/alpha/isa_traits.hh: Add in clear functions. cpu/base.cc: cpu/base.hh: Add in CPU progress event. cpu/base_dyn_inst.hh: Mimic normal registers in terms of writing/reading floats. cpu/checker/cpu.cc: cpu/checker/cpu.hh: cpu/checker/cpu_builder.cc: cpu/checker/o3_cpu_builder.cc: Fix up stuff. cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: Bring up to speed with newmem. cpu/o3/alpha_cpu_builder.cc: Allow for progress intervals. cpu/o3/tournament_pred.cc: Fix up predictor. cpu/o3/tournament_pred.hh: cpu/ozone/cpu.hh: cpu/ozone/cpu_impl.hh: cpu/simple/cpu.cc: Fixes. cpu/ozone/cpu_builder.cc: Allow progress interval. cpu/ozone/front_end_impl.hh: Comment out this message. cpu/ozone/lw_back_end_impl.hh: Remove this. python/m5/objects/BaseCPU.py: Add progress interval. python/m5/objects/Root.py: Allow for stat reset. sim/serialize.cc: sim/stat_control.cc: Add in stats reset. --HG-- extra : convert_revision : fdb5ac5542099173cc30c40ea93372a065534b5e |
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.. | ||
back_end.cc | ||
back_end.hh | ||
back_end_impl.hh | ||
cpu.cc | ||
cpu.hh | ||
cpu_builder.cc | ||
cpu_impl.hh | ||
dyn_inst.cc | ||
dyn_inst.hh | ||
dyn_inst_impl.hh | ||
ea_list.cc | ||
ea_list.hh | ||
front_end.cc | ||
front_end.hh | ||
front_end_impl.hh | ||
inorder_back_end.cc | ||
inorder_back_end.hh | ||
inorder_back_end_impl.hh | ||
inst_queue.cc | ||
inst_queue.hh | ||
inst_queue_impl.hh | ||
lsq_unit.cc | ||
lsq_unit.hh | ||
lsq_unit_impl.hh | ||
lw_back_end.cc | ||
lw_back_end.hh | ||
lw_back_end_impl.hh | ||
lw_lsq.cc | ||
lw_lsq.hh | ||
lw_lsq_impl.hh | ||
null_predictor.hh | ||
ozone_impl.hh | ||
rename_table.cc | ||
rename_table.hh | ||
rename_table_impl.hh | ||
simple_impl.hh | ||
simple_params.hh | ||
thread_state.hh |