1131 lines
131 KiB
Text
1131 lines
131 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.172545 # Number of seconds simulated
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sim_ticks 1172544977000 # Number of ticks simulated
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final_tick 1172544977000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 706392 # Simulator instruction rate (inst/s)
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host_op_rate 900233 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 13469238975 # Simulator tick rate (ticks/s)
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host_mem_usage 389548 # Number of bytes of host memory used
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host_seconds 87.05 # Real time elapsed on the host
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sim_insts 61493926 # Number of instructions simulated
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sim_ops 78368454 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
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|
system.physmem.bytes_read::cpu0.inst 394788 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 4717236 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 322588 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 4794736 # Number of bytes read from this memory
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system.physmem.bytes_read::total 60561444 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 394788 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 322588 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 717376 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4107264 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7134608 # Number of bytes written to this memory
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system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
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|
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
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|
system.physmem.num_reads::cpu0.inst 12387 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 73779 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 5122 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 74944 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 6457695 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 64176 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
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system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 821012 # Number of write requests responded to by this memory
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system.physmem.bw_read::realview.clcd 42925132 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.inst 336693 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 4023075 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 218 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 275118 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 4089170 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 51649570 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 336693 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 275118 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 611811 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 3502863 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 14498 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 2567359 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 6084720 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 3502863 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.clcd 42925132 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s)
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|
system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 336693 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 4037573 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 218 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 275118 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 6656529 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 57734290 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
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system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
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system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
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system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
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system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
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system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 58 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 58 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s)
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system.l2c.replacements 69301 # number of replacements
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system.l2c.tagsinuse 52667.431766 # Cycle average of tags in use
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system.l2c.total_refs 1645571 # Total number of references to valid blocks.
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system.l2c.sampled_refs 134500 # Sample count of references to valid blocks.
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system.l2c.avg_refs 12.234729 # Average number of references to valid blocks.
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.l2c.occ_blocks::writebacks 39900.139395 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.dtb.walker 0.000282 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.itb.walker 0.001242 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.inst 3730.644795 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu0.data 4216.663550 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu1.dtb.walker 2.734150 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu1.inst 2763.076938 # Average occupied blocks per requestor
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system.l2c.occ_blocks::cpu1.data 2054.171414 # Average occupied blocks per requestor
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system.l2c.occ_percent::writebacks 0.608828 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu0.inst 0.056925 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu0.data 0.064341 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy
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system.l2c.occ_percent::cpu1.inst 0.042161 # Average percentage of cache occupancy
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|
system.l2c.occ_percent::cpu1.data 0.031344 # Average percentage of cache occupancy
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system.l2c.occ_percent::total 0.803641 # Average percentage of cache occupancy
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|
system.l2c.ReadReq_hits::cpu0.dtb.walker 4102 # number of ReadReq hits
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|
system.l2c.ReadReq_hits::cpu0.itb.walker 1845 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 402958 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 205810 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 5738 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 1962 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 449307 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 144268 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1215990 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 572486 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 572486 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 1132 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 588 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 1720 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 206 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 310 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 56781 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 53046 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 109827 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 4102 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 1845 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 402958 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 262591 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 5738 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 1962 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 449307 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 197314 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1325817 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 4102 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 1845 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 402958 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 262591 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 5738 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 1962 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 449307 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 197314 # number of overall hits
|
|
system.l2c.overall_hits::total 1325817 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 5755 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 7866 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 5035 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 3646 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 22309 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 4696 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 3601 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 8297 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 568 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 498 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 1066 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 67165 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 72394 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 139559 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 5755 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 75031 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 5035 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 76040 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 161868 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 5755 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 75031 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 5035 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 76040 # number of overall misses
|
|
system.l2c.overall_misses::total 161868 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 52000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 104000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 299823500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 409333998 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 208500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 262768000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 190087500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 1162377498 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 29968997 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 27317000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 57285997 # number of UpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3654000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6100000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.SCUpgradeReq_miss_latency::total 9754000 # number of SCUpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 3493697466 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 3769025494 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 7262722960 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.dtb.walker 52000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.itb.walker 104000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 299823500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 3903031464 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 208500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 262768000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 3959112994 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 8425100458 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.dtb.walker 52000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.itb.walker 104000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 299823500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 3903031464 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 208500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 262768000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 3959112994 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 8425100458 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 4103 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 1847 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.inst 408713 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 213676 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 5742 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 1962 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 454342 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 147914 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 1238299 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 572486 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 572486 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 5828 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 4189 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 10017 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 774 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 602 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 1376 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 123946 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 125440 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 249386 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 4103 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 1847 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 408713 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 337622 # number of demand (read+write) accesses
|
|
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system.l2c.overall_accesses::cpu1.dtb.walker 5742 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu1.inst 454342 # number of overall (read+write) accesses
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system.l2c.overall_accesses::cpu1.data 273354 # number of overall (read+write) accesses
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system.l2c.ReadReq_miss_rate::total 0.018016 # miss rate for ReadReq accesses
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|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.859632 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.828292 # miss rate for UpgradeReq accesses
|
|
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|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.827243 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.774709 # miss rate for SCUpgradeReq accesses
|
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|
|
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|
|
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|
|
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|
|
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|
|
system.l2c.demand_miss_rate::cpu0.inst 0.014081 # miss rate for demand accesses
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|
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system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000697 # miss rate for demand accesses
|
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system.l2c.demand_miss_rate::cpu1.inst 0.011082 # miss rate for demand accesses
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system.l2c.demand_miss_rate::cpu1.data 0.278174 # miss rate for demand accesses
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system.l2c.demand_miss_rate::total 0.108805 # miss rate for demand accesses
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system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000244 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu0.itb.walker 0.001083 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu0.inst 0.014081 # miss rate for overall accesses
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system.l2c.overall_miss_rate::cpu1.data 0.278174 # miss rate for overall accesses
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|
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system.l2c.ReadReq_avg_miss_latency::cpu1.data 52135.902359 # average ReadReq miss latency
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|
system.l2c.ReadReq_avg_miss_latency::total 52103.523152 # average ReadReq miss latency
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system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6381.813671 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7585.948348 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 6904.422924 # average UpgradeReq miss latency
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system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6433.098592 # average SCUpgradeReq miss latency
|
|
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12248.995984 # average SCUpgradeReq miss latency
|
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system.l2c.SCUpgradeReq_avg_miss_latency::total 9150.093809 # average SCUpgradeReq miss latency
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system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52016.637624 # average ReadExReq miss latency
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system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52062.677763 # average ReadExReq miss latency
|
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system.l2c.ReadExReq_avg_miss_latency::total 52040.520210 # average ReadExReq miss latency
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system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency
|
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system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52000 # average overall miss latency
|
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system.l2c.demand_avg_miss_latency::cpu0.inst 52097.914857 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52000 # average overall miss latency
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|
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system.l2c.overall_avg_miss_latency::cpu0.inst 52097.914857 # average overall miss latency
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|
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system.l2c.overall_avg_miss_latency::cpu1.inst 52188.282026 # average overall miss latency
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system.l2c.overall_avg_miss_latency::cpu1.data 52066.188769 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 52049.203413 # average overall miss latency
|
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
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system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
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system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
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|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
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system.l2c.fast_writes 0 # number of fast writes performed
|
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|
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system.l2c.writebacks::total 64176 # number of writebacks
|
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|
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|
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|
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system.l2c.ReadReq_mshr_uncacheable_latency::total 131741656499 # number of ReadReq MSHR uncacheable cycles
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system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 694839000 # number of WriteReq MSHR uncacheable cycles
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system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for ReadReq accesses
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|
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|
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|
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|
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|
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|
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system.l2c.UpgradeReq_mshr_miss_rate::total 0.828292 # mshr miss rate for UpgradeReq accesses
|
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|
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|
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system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.774709 # mshr miss rate for SCUpgradeReq accesses
|
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|
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system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577121 # mshr miss rate for ReadExReq accesses
|
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|
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|
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|
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|
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|
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|
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system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for overall accesses
|
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|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000697 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.278174 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.108805 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40037.757437 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40135.216676 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 40104.043393 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.090290 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40068.036656 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40047.125467 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40052.816901 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40066.265060 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40059.099437 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40015.975583 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40062.463740 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40040.090571 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40018.259120 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40065.952130 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 40048.904347 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40018.259120 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40065.952130 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 40048.904347 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 7082876 # DTB read hits
|
|
system.cpu0.dtb.read_misses 3736 # DTB read misses
|
|
system.cpu0.dtb.write_hits 5665319 # DTB write hits
|
|
system.cpu0.dtb.write_misses 804 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 1790 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 7086612 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 5666123 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 12748195 # DTB hits
|
|
system.cpu0.dtb.misses 4540 # DTB misses
|
|
system.cpu0.dtb.accesses 12752735 # DTB accesses
|
|
system.cpu0.itb.inst_hits 29606138 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 2205 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 29608343 # ITB inst accesses
|
|
system.cpu0.itb.hits 29606138 # DTB hits
|
|
system.cpu0.itb.misses 2205 # DTB misses
|
|
system.cpu0.itb.accesses 29608343 # DTB accesses
|
|
system.cpu0.numCycles 2345089954 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.committedInsts 28907917 # Number of instructions committed
|
|
system.cpu0.committedOps 37265600 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 33149705 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 1243107 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 4358822 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 33149705 # number of integer instructions
|
|
system.cpu0.num_fp_insts 3860 # number of float instructions
|
|
system.cpu0.num_int_register_reads 190344582 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 36275228 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
|
|
system.cpu0.num_mem_refs 13418689 # number of memory refs
|
|
system.cpu0.num_load_insts 7420825 # Number of load instructions
|
|
system.cpu0.num_store_insts 5997864 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 2204555139.350120 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 140534814.649880 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.059927 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.940073 # Percentage of idle cycles
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 46687 # number of quiesce instructions executed
|
|
system.cpu0.icache.replacements 408797 # number of replacements
|
|
system.cpu0.icache.tagsinuse 509.495989 # Cycle average of tags in use
|
|
system.cpu0.icache.total_refs 29196812 # Total number of references to valid blocks.
|
|
system.cpu0.icache.sampled_refs 409309 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.avg_refs 71.331957 # Average number of references to valid blocks.
|
|
system.cpu0.icache.warmup_cycle 75128897000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.occ_blocks::cpu0.inst 509.495989 # Average occupied blocks per requestor
|
|
system.cpu0.icache.occ_percent::cpu0.inst 0.995109 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_percent::total 0.995109 # Average percentage of cache occupancy
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 29196812 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 29196812 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 29196812 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 29196812 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 29196812 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 29196812 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 409309 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 409309 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 409309 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 409309 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 409309 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 409309 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6108172000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 6108172000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 6108172000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 6108172000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 6108172000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 6108172000 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 29606121 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 29606121 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 29606121 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 29606121 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 29606121 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 29606121 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013825 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.013825 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013825 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.013825 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013825 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.013825 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14923.131424 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 14923.131424 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14923.131424 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 14923.131424 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14923.131424 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 14923.131424 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 409309 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 409309 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 409309 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 409309 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 409309 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 409309 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4879387500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4879387500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4879387500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 4879387500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4879387500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 4879387500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013825 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013825 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013825 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.013825 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013825 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.013825 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11921.036430 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11921.036430 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11921.036430 # average overall mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.replacements 330813 # number of replacements
|
|
system.cpu0.dcache.tagsinuse 457.939353 # Cycle average of tags in use
|
|
system.cpu0.dcache.total_refs 12292528 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.sampled_refs 331325 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.avg_refs 37.101118 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.warmup_cycle 664264000 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.occ_blocks::cpu0.data 457.939353 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.occ_percent::cpu0.data 0.894413 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::total 0.894413 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6612408 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 6612408 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 5360091 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 5360091 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147992 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 147992 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149726 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 149726 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 11972499 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 11972499 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 11972499 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 11972499 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 228125 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 228125 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 141749 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 141749 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9279 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 9279 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7492 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 7492 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 369874 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 369874 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 369874 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 369874 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443081500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 3443081500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4917870500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 4917870500 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100339500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 100339500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74628000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 74628000 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 8360952000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 8360952000 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 8360952000 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 8360952000 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 6840533 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 6840533 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5501840 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 5501840 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157271 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 157271 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157218 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 157218 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 12342373 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 12342373 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 12342373 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 12342373 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033349 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.033349 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025764 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.025764 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059000 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059000 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047654 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047654 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029968 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.029968 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029968 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.029968 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15092.960000 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15092.960000 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34694.216538 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 34694.216538 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10813.611381 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10813.611381 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9961.025093 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9961.025093 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22604.865441 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 22604.865441 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22604.865441 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 22604.865441 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 306322 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 306322 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228125 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 228125 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141749 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 141749 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9279 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9279 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7485 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 7485 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 369874 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 369874 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 369874 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 369874 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758091164 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758091164 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4492431566 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4492431566 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72483506 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72483506 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52154019 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52154019 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7250522730 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 7250522730 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7250522730 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 7250522730 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10425846000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10425846000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 819721500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 819721500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11245567500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11245567500 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033349 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033349 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059000 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059000 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047609 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047609 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029968 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.029968 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029968 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.029968 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12090.262637 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12090.262637 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31692.862496 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31692.862496 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7811.564393 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7811.564393 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6967.804810 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6967.804810 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19602.682887 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19602.682887 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19602.682887 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19602.682887 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 8314117 # DTB read hits
|
|
system.cpu1.dtb.read_misses 3669 # DTB read misses
|
|
system.cpu1.dtb.write_hits 5830380 # DTB write hits
|
|
system.cpu1.dtb.write_misses 1436 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 8317786 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 5831816 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 14144497 # DTB hits
|
|
system.cpu1.dtb.misses 5105 # DTB misses
|
|
system.cpu1.dtb.accesses 14149602 # DTB accesses
|
|
system.cpu1.itb.inst_hits 33196626 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 2171 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 33198797 # ITB inst accesses
|
|
system.cpu1.itb.hits 33196626 # DTB hits
|
|
system.cpu1.itb.misses 2171 # DTB misses
|
|
system.cpu1.itb.accesses 33198797 # DTB accesses
|
|
system.cpu1.numCycles 2343593518 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 32586009 # Number of instructions committed
|
|
system.cpu1.committedOps 41102854 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 37326288 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 962171 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 3714570 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 37326288 # number of integer instructions
|
|
system.cpu1.num_fp_insts 6793 # number of float instructions
|
|
system.cpu1.num_int_register_reads 213739964 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 39466250 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
|
|
system.cpu1.num_mem_refs 14682267 # number of memory refs
|
|
system.cpu1.num_load_insts 8636040 # Number of load instructions
|
|
system.cpu1.num_store_insts 6046227 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 1858750530.714142 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 484842987.285858 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.206880 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.793120 # Percentage of idle cycles
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 43921 # number of quiesce instructions executed
|
|
system.cpu1.icache.replacements 454393 # number of replacements
|
|
system.cpu1.icache.tagsinuse 478.384673 # Cycle average of tags in use
|
|
system.cpu1.icache.total_refs 32741717 # Total number of references to valid blocks.
|
|
system.cpu1.icache.sampled_refs 454905 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.avg_refs 71.974845 # Average number of references to valid blocks.
|
|
system.cpu1.icache.warmup_cycle 92994898000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.occ_blocks::cpu1.inst 478.384673 # Average occupied blocks per requestor
|
|
system.cpu1.icache.occ_percent::cpu1.inst 0.934345 # Average percentage of cache occupancy
|
|
system.cpu1.icache.occ_percent::total 0.934345 # Average percentage of cache occupancy
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 32741717 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 32741717 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 32741717 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 32741717 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 32741717 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 32741717 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 454905 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 454905 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 454905 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 454905 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 454905 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 454905 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6718353500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 6718353500 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 6718353500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 6718353500 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 6718353500 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 6718353500 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 33196622 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 33196622 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 33196622 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 33196622 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 33196622 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 33196622 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013703 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.013703 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013703 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.013703 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013703 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.013703 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.695662 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.695662 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.695662 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 14768.695662 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.695662 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 14768.695662 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454905 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 454905 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 454905 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 454905 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 454905 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 454905 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5352734000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5352734000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5352734000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 5352734000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5352734000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 5352734000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013703 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013703 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013703 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.013703 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013703 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.013703 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.707334 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.707334 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.707334 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.707334 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.707334 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.707334 # average overall mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
|
|
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.replacements 292476 # number of replacements
|
|
system.cpu1.dcache.tagsinuse 472.237187 # Cycle average of tags in use
|
|
system.cpu1.dcache.total_refs 11966907 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.sampled_refs 292816 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.avg_refs 40.868351 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.warmup_cycle 84138671000 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.occ_blocks::cpu1.data 472.237187 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.occ_percent::cpu1.data 0.922338 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.occ_percent::total 0.922338 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 6949314 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 6949314 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 4829723 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 4829723 # number of WriteReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81817 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 81817 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82772 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 82772 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 11779037 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 11779037 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 11779037 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 11779037 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 170766 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 170766 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 150259 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 150259 # number of WriteReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11112 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 11112 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10077 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 10077 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 321025 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 321025 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 321025 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 321025 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2375372000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 2375372000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 5143695000 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 5143695000 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 106521500 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 106521500 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 88394000 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 88394000 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 7519067000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 7519067000 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 7519067000 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 7519067000 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 7120080 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 7120080 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 4979982 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 4979982 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92929 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 92929 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92849 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 92849 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 12100062 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 12100062 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 12100062 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 12100062 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023984 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.023984 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030173 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.030173 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119575 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119575 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108531 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108531 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026531 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.026531 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026531 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.026531 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13910.099200 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13910.099200 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34232.192414 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 34232.192414 # average WriteReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9586.168107 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9586.168107 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8771.856703 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8771.856703 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23422.060587 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 23422.060587 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23422.060587 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 23422.060587 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.writebacks::writebacks 266164 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 266164 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170766 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 170766 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150259 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 150259 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11112 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11112 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10067 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 10067 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 321025 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 321025 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 321025 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 321025 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1862452631 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1862452631 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4692688176 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4692688176 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73165002 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73165002 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 58182011 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 58182011 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6555140807 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 6555140807 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6555140807 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 6555140807 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136477204500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136477204500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39709759000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39709759000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176186963500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176186963500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023984 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023984 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030173 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030173 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119575 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119575 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108423 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108423 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026531 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.026531 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026531 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.026531 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10906.460484 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10906.460484 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31230.662895 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31230.662895 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6584.323434 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6584.323434 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5779.478593 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5779.478593 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20419.409102 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20419.409102 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20419.409102 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20419.409102 # average overall mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.avg_refs nan # Average number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550791407487 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.ReadReq_mshr_uncacheable_latency::total 550791407487 # number of ReadReq MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550791407487 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_latency::total 550791407487 # number of overall MSHR uncacheable cycles
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
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