89ea323250
Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
220 lines
24 KiB
Text
220 lines
24 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1619389 # Simulator instruction rate (inst/s)
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host_mem_usage 199040 # Number of bytes of host memory used
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host_seconds 0.31 # Real time elapsed on the host
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host_tick_rate 2386410783 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 500001 # Number of instructions simulated
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sim_seconds 0.000737 # Number of seconds simulated
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sim_ticks 737389000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 17640000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 16695000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 56029 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 17416000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 16483000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 180149 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 35056000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.003463 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 626 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 33178000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.003463 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 626 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 180149 # number of overall hits
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system.cpu.dcache.overall_miss_latency 35056000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.003463 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 626 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 33178000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.003463 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 626 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 286.463742 # Cycle average of tags in use
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system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 0 # number of writebacks
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system.cpu.dtb.accesses 180793 # DTB accesses
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system.cpu.dtb.acv 0 # DTB access violations
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system.cpu.dtb.hits 180775 # DTB hits
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system.cpu.dtb.misses 18 # DTB misses
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system.cpu.dtb.read_accesses 124443 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 124435 # DTB read hits
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system.cpu.dtb.read_misses 8 # DTB read misses
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system.cpu.dtb.write_accesses 56350 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 56340 # DTB write hits
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system.cpu.dtb.write_misses 10 # DTB write misses
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system.cpu.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 499617 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 22568000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 21359000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 500020 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.icache.demand_hits 499617 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 22568000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses
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system.cpu.icache.demand_misses 403 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 21359000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 499617 # number of overall hits
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system.cpu.icache.overall_miss_latency 22568000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses
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system.cpu.icache.overall_misses 403 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 21359000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 264.328816 # Cycle average of tags in use
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system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.accesses 500033 # ITB accesses
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system.cpu.itb.acv 0 # ITB acv
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system.cpu.itb.hits 500020 # ITB hits
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system.cpu.itb.misses 13 # ITB misses
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system.cpu.l2cache.ReadExReq_accesses 139 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_latency 7228000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 139 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 5560000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 139 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 718 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_miss_latency 37336000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 718 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 28720000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses
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system.cpu.l2cache.UpgradeReq_accesses 172 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_latency 8944000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_misses 172 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6880000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_misses 172 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 44564000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 34280000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 0 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 44564000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 857 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 34280000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.sampled_refs 546 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 370.220381 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 0 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 1474778 # number of cpu cycles simulated
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system.cpu.num_insts 500001 # Number of instructions executed
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system.cpu.num_refs 182222 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
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---------- End Simulation Statistics ----------
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