89ea323250
Prefetching is not enabled in any of our regressions, so no significant stat values have changed, but zero-valued prefetch stats no longer show up when prefetching is disabled so there are noticable changes in the reference stat files anyway.
638 lines
69 KiB
Text
638 lines
69 KiB
Text
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 6937900 # Number of BTB hits
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global.BPredUnit.BTBLookups 13339861 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 41537 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 828629 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 12132448 # Number of conditional branches predicted
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global.BPredUnit.lookups 14570242 # Number of BP lookups
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global.BPredUnit.usedRAS 1034900 # Number of times the RAS was used to get a target.
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host_inst_rate 209657 # Simulator instruction rate (inst/s)
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host_mem_usage 292968 # Number of bytes of host memory used
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host_seconds 253.23 # Real time elapsed on the host
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host_tick_rate 7374290880 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 3083644 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 2877472 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 11055097 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 7027136 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 53090630 # Number of instructions simulated
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sim_seconds 1.867363 # Number of seconds simulated
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sim_ticks 1867363148500 # Number of ticks simulated
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system.cpu.commit.COM:branches 8461943 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 974606 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 100617513
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 76371867 7590.32%
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1 10755813 1068.98%
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2 5991818 595.50%
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3 2987930 296.96%
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4 2074332 206.16%
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5 671621 66.75%
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6 397219 39.48%
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7 392307 38.99%
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8 974606 96.86%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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system.cpu.commit.COM:count 56284983 # Number of instructions committed
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system.cpu.commit.COM:loads 9308629 # Number of loads committed
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system.cpu.commit.COM:membars 228003 # Number of memory barriers committed
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system.cpu.commit.COM:refs 15700868 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 787164 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 56284983 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 667781 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 9518126 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 53090630 # Number of Instructions Simulated
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system.cpu.committedInsts_total 53090630 # Number of Instructions Simulated
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system.cpu.cpi 2.580435 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 2.580435 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 214297 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_avg_miss_latency 15516.058460 # average LoadLockedReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11817.323059 # average LoadLockedReq mshr miss latency
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system.cpu.dcache.LoadLockedReq_hits 192128 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_latency 343975500 # number of LoadLockedReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_rate 0.103450 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses 22169 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_mshr_hits 4649 # number of LoadLockedReq MSHR hits
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system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207039500 # number of LoadLockedReq MSHR miss cycles
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system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.081756 # mshr miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_mshr_misses 17520 # number of LoadLockedReq MSHR misses
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system.cpu.dcache.ReadReq_accesses 9342423 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 23886.371687 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22764.504418 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.cpu.dcache.ReadReq_hits 7809504 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 36615873000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.164082 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 1532919 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 448215 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 24692749000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.116105 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 1084704 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904972000 # number of ReadReq MSHR uncacheable cycles
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system.cpu.dcache.StoreCondReq_accesses 219789 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_avg_miss_latency 56331.265633 # average StoreCondReq miss latency
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system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53331.265633 # average StoreCondReq mshr miss latency
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system.cpu.dcache.StoreCondReq_hits 189804 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_miss_latency 1689093000 # number of StoreCondReq miss cycles
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system.cpu.dcache.StoreCondReq_miss_rate 0.136426 # miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_misses 29985 # number of StoreCondReq misses
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system.cpu.dcache.StoreCondReq_mshr_miss_latency 1599138000 # number of StoreCondReq MSHR miss cycles
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system.cpu.dcache.StoreCondReq_mshr_miss_rate 0.136426 # mshr miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_mshr_misses 29985 # number of StoreCondReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 6157295 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 49032.528329 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54492.949680 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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system.cpu.dcache.WriteReq_hits 3927003 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 109356855672 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.362219 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 2230292 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1833354 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 21630322460 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.064466 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 396938 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235426497 # number of WriteReq MSHR uncacheable cycles
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system.cpu.dcache.avg_blocked_cycles_no_mshrs 10009.885310 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 11500 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 8.828407 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 138181 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 2 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 1383175962 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 23000 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 15499718 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 38789.408479 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 31264.685707 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 11736507 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 145972728672 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.242792 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 3763211 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2281569 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 46323071460 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.095592 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 1481642 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 15499718 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 38789.408479 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 31264.685707 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 11736507 # number of overall hits
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system.cpu.dcache.overall_miss_latency 145972728672 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.242792 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 3763211 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2281569 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 46323071460 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.095592 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 1481642 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 2140398497 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 1401991 # number of replacements
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system.cpu.dcache.sampled_refs 1402503 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 511.995429 # Cycle average of tags in use
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system.cpu.dcache.total_refs 12381868 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 21439000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 430428 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 48410304 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 42525 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 614935 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 72780900 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 37979006 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 13077120 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 1650418 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 134762 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 1151082 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 1236420 # DTB accesses
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system.cpu.dtb.acv 825 # DTB access violations
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system.cpu.dtb.hits 16772347 # DTB hits
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system.cpu.dtb.misses 44495 # DTB misses
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system.cpu.dtb.read_accesses 910052 # DTB read accesses
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system.cpu.dtb.read_acv 586 # DTB read access violations
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system.cpu.dtb.read_hits 10174508 # DTB read hits
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system.cpu.dtb.read_misses 36219 # DTB read misses
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system.cpu.dtb.write_accesses 326368 # DTB write accesses
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system.cpu.dtb.write_acv 239 # DTB write access violations
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system.cpu.dtb.write_hits 6597839 # DTB write hits
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system.cpu.dtb.write_misses 8276 # DTB write misses
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system.cpu.fetch.Branches 14570242 # Number of branches that fetch encountered
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system.cpu.fetch.CacheLines 9007841 # Number of cache lines fetched
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system.cpu.fetch.Cycles 23500316 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.IcacheSquashes 455597 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.Insts 74326781 # Number of instructions fetch has processed
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system.cpu.fetch.MiscStallCycles 2461 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.SquashCycles 969865 # Number of cycles fetch has spent squashing
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system.cpu.fetch.branchRate 0.106355 # Number of branch fetches per cycle
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system.cpu.fetch.icacheStallCycles 9007841 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.predictedBranches 7972800 # Number of branches that fetch has predicted taken
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system.cpu.fetch.rate 0.542543 # Number of inst fetches per cycle
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system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist.samples 102267931
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system.cpu.fetch.rateDist.min_value 0
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0 87815810 8586.84%
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1 1050742 102.74%
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2 2021882 197.70%
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3 969421 94.79%
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4 3003437 293.68%
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5 686434 67.12%
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6 832579 81.41%
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7 1218388 119.14%
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8 4669238 456.57%
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system.cpu.fetch.rateDist.max_value 8
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system.cpu.fetch.rateDist.end_dist
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system.cpu.icache.ReadReq_accesses 9007841 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 14905.597019 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 11907.422251 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 7960337 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 15613672500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.116288 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 1047504 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_hits 51957 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_latency 11854398500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.110520 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 995547 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles_no_mshrs 11175.438596 # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 7.997460 # Average number of references to valid blocks.
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system.cpu.icache.blocked_no_mshrs 57 # number of cycles access was blocked
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system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_mshrs 637000 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 9007841 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 14905.597019 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 11907.422251 # average overall mshr miss latency
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system.cpu.icache.demand_hits 7960337 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 15613672500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.116288 # miss rate for demand accesses
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system.cpu.icache.demand_misses 1047504 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 51957 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 11854398500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.110520 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 995547 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 9007841 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 14905.597019 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 11907.422251 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 7960337 # number of overall hits
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system.cpu.icache.overall_miss_latency 15613672500 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.116288 # miss rate for overall accesses
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system.cpu.icache.overall_misses 1047504 # number of overall misses
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system.cpu.icache.overall_mshr_hits 51957 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 11854398500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.110520 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 995547 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 994847 # number of replacements
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system.cpu.icache.sampled_refs 995358 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 509.772456 # Cycle average of tags in use
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system.cpu.icache.total_refs 7960336 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 25306164000 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idleCycles 34729008 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.iew.EXEC:branches 9164699 # Number of branches executed
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system.cpu.iew.EXEC:nop 3680668 # number of nop insts executed
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system.cpu.iew.EXEC:rate 0.420415 # Inst execution rate
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system.cpu.iew.EXEC:refs 17055609 # number of memory reference insts executed
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system.cpu.iew.EXEC:stores 6621040 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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system.cpu.iew.WB:consumers 34548488 # num instructions consuming a value
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system.cpu.iew.WB:count 57002857 # cumulative count of insts written-back
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system.cpu.iew.WB:fanout 0.763990 # average fanout of values written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
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system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.WB:producers 26394693 # num instructions producing a value
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system.cpu.iew.WB:rate 0.416089 # insts written-back per cycle
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system.cpu.iew.WB:sent 57104330 # cumulative count of insts sent to commit
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system.cpu.iew.branchMispredicts 856523 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewBlockCycles 9726576 # Number of cycles IEW is blocking
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system.cpu.iew.iewDispLoadInsts 11055097 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 1799800 # Number of dispatched non-speculative instructions
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|
system.cpu.iew.iewDispSquashedInsts 1048637 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispStoreInsts 7027136 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispatchedInsts 65932751 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewExecLoadInsts 10434569 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 539744 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.iewExecutedInsts 57595615 # Number of executed instructions
|
|
system.cpu.iew.iewIQFullEvents 50922 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewLSQFullEvents 6567 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.iewSquashCycles 1650418 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewUnblockCycles 550443 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread.0.cacheBlocked 311143 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.lsq.thread.0.forwLoads 426303 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread.0.ignoredResponses 11520 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread.0.memOrderViolation 46025 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread.0.rescheduledLoads 15352 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread.0.squashedLoads 1746468 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread.0.squashedStores 634897 # Number of stores squashed
|
|
system.cpu.iew.memOrderViolationEvents 46025 # Number of memory order violations
|
|
system.cpu.iew.predictedNotTakenIncorrect 380989 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.predictedTakenIncorrect 475534 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.ipc 0.387532 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.387532 # IPC: Total IPC of All Threads
|
|
system.cpu.iq.ISSUE:FU_type_0 58135361 # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|
No_OpClass 7284 0.01% # Type of FU issued
|
|
IntAlu 39619390 68.15% # Type of FU issued
|
|
IntMult 62115 0.11% # Type of FU issued
|
|
IntDiv 0 0.00% # Type of FU issued
|
|
FloatAdd 25609 0.04% # Type of FU issued
|
|
FloatCmp 0 0.00% # Type of FU issued
|
|
FloatCvt 0 0.00% # Type of FU issued
|
|
FloatMult 0 0.00% # Type of FU issued
|
|
FloatDiv 3636 0.01% # Type of FU issued
|
|
FloatSqrt 0 0.00% # Type of FU issued
|
|
MemRead 10789898 18.56% # Type of FU issued
|
|
MemWrite 6674141 11.48% # Type of FU issued
|
|
IprAccess 953288 1.64% # Type of FU issued
|
|
InstPrefetch 0 0.00% # Type of FU issued
|
|
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
|
system.cpu.iq.ISSUE:fu_busy_cnt 434481 # FU busy when requested
|
|
system.cpu.iq.ISSUE:fu_busy_rate 0.007474 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.ISSUE:fu_full.start_dist
|
|
No_OpClass 0 0.00% # attempts to use FU when none available
|
|
IntAlu 52045 11.98% # attempts to use FU when none available
|
|
IntMult 0 0.00% # attempts to use FU when none available
|
|
IntDiv 0 0.00% # attempts to use FU when none available
|
|
FloatAdd 0 0.00% # attempts to use FU when none available
|
|
FloatCmp 0 0.00% # attempts to use FU when none available
|
|
FloatCvt 0 0.00% # attempts to use FU when none available
|
|
FloatMult 0 0.00% # attempts to use FU when none available
|
|
FloatDiv 0 0.00% # attempts to use FU when none available
|
|
FloatSqrt 0 0.00% # attempts to use FU when none available
|
|
MemRead 278817 64.17% # attempts to use FU when none available
|
|
MemWrite 103619 23.85% # attempts to use FU when none available
|
|
IprAccess 0 0.00% # attempts to use FU when none available
|
|
InstPrefetch 0 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.ISSUE:fu_full.end_dist
|
|
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
|
system.cpu.iq.ISSUE:issued_per_cycle.samples 102267931
|
|
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
|
0 73151138 7152.89%
|
|
1 14628619 1430.42%
|
|
2 6419666 627.73%
|
|
3 3934330 384.71%
|
|
4 2528894 247.28%
|
|
5 1032607 100.97%
|
|
6 444582 43.47%
|
|
7 106443 10.41%
|
|
8 21652 2.12%
|
|
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
|
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
|
|
|
system.cpu.iq.ISSUE:rate 0.424355 # Inst issue rate
|
|
system.cpu.iq.iqInstsAdded 60200389 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqInstsIssued 58135361 # Number of instructions issued
|
|
system.cpu.iq.iqNonSpecInstsAdded 2051694 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqSquashedInstsExamined 8738375 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedInstsIssued 34584 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 1383913 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.iqSquashedOperandsExamined 4729371 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.itb.accesses 1303895 # ITB accesses
|
|
system.cpu.itb.acv 943 # ITB acv
|
|
system.cpu.itb.hits 1264480 # ITB hits
|
|
system.cpu.itb.misses 39415 # ITB misses
|
|
system.cpu.kern.callpal 192656 # number of callpals executed
|
|
system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu.kern.callpal_swpctx 4177 2.17% 2.17% # number of callpals executed
|
|
system.cpu.kern.callpal_tbi 54 0.03% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal_wrent 7 0.00% 2.20% # number of callpals executed
|
|
system.cpu.kern.callpal_swpipl 175684 91.19% 93.39% # number of callpals executed
|
|
system.cpu.kern.callpal_rdps 6794 3.53% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal_wrkgp 1 0.00% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal_wrusp 7 0.00% 96.92% # number of callpals executed
|
|
system.cpu.kern.callpal_rdusp 9 0.00% 96.93% # number of callpals executed
|
|
system.cpu.kern.callpal_whami 2 0.00% 96.93% # number of callpals executed
|
|
system.cpu.kern.callpal_rti 5221 2.71% 99.64% # number of callpals executed
|
|
system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed
|
|
system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.hwrei 211815 # number of hwrei instructions executed
|
|
system.cpu.kern.inst.quiesce 6383 # number of quiesce instructions executed
|
|
system.cpu.kern.ipl_count 183033 # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count_0 74957 40.95% 40.95% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count_21 237 0.13% 41.08% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count_22 1890 1.03% 42.11% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_count_31 105949 57.89% 100.00% # number of times we switched to this ipl
|
|
system.cpu.kern.ipl_good 149307 # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good_0 73590 49.29% 49.29% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good_21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good_22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_good_31 73590 49.29% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu.kern.ipl_ticks 1867362274000 # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks_0 1824759658500 97.72% 97.72% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks_21 102563000 0.01% 97.72% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks_22 392423000 0.02% 97.75% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_ticks_31 42107629500 2.25% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu.kern.ipl_used_0 0.981763 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.ipl_used_31 0.694579 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu.kern.mode_good_kernel 1911
|
|
system.cpu.kern.mode_good_user 1741
|
|
system.cpu.kern.mode_good_idle 170
|
|
system.cpu.kern.mode_switch_kernel 5973 # number of protection mode switches
|
|
system.cpu.kern.mode_switch_user 1741 # number of protection mode switches
|
|
system.cpu.kern.mode_switch_idle 2095 # number of protection mode switches
|
|
system.cpu.kern.mode_switch_good 1.401085 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good_kernel 0.319940 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_switch_good_idle 0.081146 # fraction of useful protection mode switches
|
|
system.cpu.kern.mode_ticks_kernel 31312997500 1.68% 1.68% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks_user 3190588500 0.17% 1.85% # number of ticks spent at the given mode
|
|
system.cpu.kern.mode_ticks_idle 1832858680000 98.15% 100.00% # number of ticks spent at the given mode
|
|
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
|
system.cpu.kern.syscall 326 # number of syscalls executed
|
|
system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed
|
|
system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed
|
|
system.cpu.kern.syscall_4 4 1.23% 12.88% # number of syscalls executed
|
|
system.cpu.kern.syscall_6 42 12.88% 25.77% # number of syscalls executed
|
|
system.cpu.kern.syscall_12 1 0.31% 26.07% # number of syscalls executed
|
|
system.cpu.kern.syscall_15 1 0.31% 26.38% # number of syscalls executed
|
|
system.cpu.kern.syscall_17 15 4.60% 30.98% # number of syscalls executed
|
|
system.cpu.kern.syscall_19 10 3.07% 34.05% # number of syscalls executed
|
|
system.cpu.kern.syscall_20 6 1.84% 35.89% # number of syscalls executed
|
|
system.cpu.kern.syscall_23 4 1.23% 37.12% # number of syscalls executed
|
|
system.cpu.kern.syscall_24 6 1.84% 38.96% # number of syscalls executed
|
|
system.cpu.kern.syscall_33 11 3.37% 42.33% # number of syscalls executed
|
|
system.cpu.kern.syscall_41 2 0.61% 42.94% # number of syscalls executed
|
|
system.cpu.kern.syscall_45 54 16.56% 59.51% # number of syscalls executed
|
|
system.cpu.kern.syscall_47 6 1.84% 61.35% # number of syscalls executed
|
|
system.cpu.kern.syscall_48 10 3.07% 64.42% # number of syscalls executed
|
|
system.cpu.kern.syscall_54 10 3.07% 67.48% # number of syscalls executed
|
|
system.cpu.kern.syscall_58 1 0.31% 67.79% # number of syscalls executed
|
|
system.cpu.kern.syscall_59 7 2.15% 69.94% # number of syscalls executed
|
|
system.cpu.kern.syscall_71 54 16.56% 86.50% # number of syscalls executed
|
|
system.cpu.kern.syscall_73 3 0.92% 87.42% # number of syscalls executed
|
|
system.cpu.kern.syscall_74 16 4.91% 92.33% # number of syscalls executed
|
|
system.cpu.kern.syscall_87 1 0.31% 92.64% # number of syscalls executed
|
|
system.cpu.kern.syscall_90 3 0.92% 93.56% # number of syscalls executed
|
|
system.cpu.kern.syscall_92 9 2.76% 96.32% # number of syscalls executed
|
|
system.cpu.kern.syscall_97 2 0.61% 96.93% # number of syscalls executed
|
|
system.cpu.kern.syscall_98 2 0.61% 97.55% # number of syscalls executed
|
|
system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed
|
|
system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed
|
|
system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed
|
|
system.cpu.numCycles 136996939 # number of cpu cycles simulated
|
|
system.cpu.rename.RENAME:BlockCycles 14276861 # Number of cycles rename is blocking
|
|
system.cpu.rename.RENAME:CommittedMaps 38259280 # Number of HB maps that are committed
|
|
system.cpu.rename.RENAME:IQFullEvents 1099460 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.RENAME:IdleCycles 39573188 # Number of cycles rename is idle
|
|
system.cpu.rename.RENAME:LSQFullEvents 2235524 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RENAME:ROBFullEvents 15708 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.RENAME:RenameLookups 83522905 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.RENAME:RenamedInsts 68741813 # Number of instructions processed by rename
|
|
system.cpu.rename.RENAME:RenamedOperands 46071316 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RENAME:RunCycles 12717646 # Number of cycles rename is running
|
|
system.cpu.rename.RENAME:SquashCycles 1650418 # Number of cycles rename is squashing
|
|
system.cpu.rename.RENAME:UnblockCycles 5220588 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RENAME:UndoneMaps 7812034 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.RENAME:serializeStallCycles 28829228 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RENAME:serializingInsts 1704991 # count of serializing insts renamed
|
|
system.cpu.rename.RENAME:skidInsts 12807732 # count of insts added to the skid buffer
|
|
system.cpu.rename.RENAME:tempSerializingInsts 256915 # count of temporary serializing insts renamed
|
|
system.cpu.timesIdled 1321478 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iocache.ReadReq_accesses 173 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_avg_miss_latency 115277.445087 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency 63277.445087 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_miss_latency 19942998 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_misses 173 # number of ReadReq misses
|
|
system.iocache.ReadReq_mshr_miss_latency 10946998 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_avg_miss_latency 137802.098720 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency 85798.754910 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_miss_latency 5725952806 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_misses 41552 # number of WriteReq misses
|
|
system.iocache.WriteReq_mshr_miss_latency 3565109864 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_rate 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
|
|
system.iocache.avg_blocked_cycles_no_mshrs 6162.652539 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.iocache.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.blocked_no_mshrs 10476 # number of cycles access was blocked
|
|
system.iocache.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles_no_mshrs 64559948 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.demand_accesses 41725 # number of demand (read+write) accesses
|
|
system.iocache.demand_avg_miss_latency 137708.707106 # average overall miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency 85705.377160 # average overall mshr miss latency
|
|
system.iocache.demand_hits 0 # number of demand (read+write) hits
|
|
system.iocache.demand_miss_latency 5745895804 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_rate 1 # miss rate for demand accesses
|
|
system.iocache.demand_misses 41725 # number of demand (read+write) misses
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.iocache.demand_mshr_miss_latency 3576056862 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.overall_accesses 41725 # number of overall (read+write) accesses
|
|
system.iocache.overall_avg_miss_latency 137708.707106 # average overall miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency 85705.377160 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
|
system.iocache.overall_hits 0 # number of overall hits
|
|
system.iocache.overall_miss_latency 5745895804 # number of overall miss cycles
|
|
system.iocache.overall_miss_rate 1 # miss rate for overall accesses
|
|
system.iocache.overall_misses 41725 # number of overall misses
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.iocache.overall_mshr_miss_latency 3576056862 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.iocache.replacements 41685 # number of replacements
|
|
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.iocache.tagsinuse 1.267414 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.warmup_cycle 1716180054000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.writebacks 41512 # number of writebacks
|
|
system.l2c.ReadExReq_accesses 300588 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_avg_miss_latency 52362.011561 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency 40213.127257 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_miss_latency 15739392331 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_misses 300588 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_mshr_miss_latency 12087583496 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_misses 300588 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadReq_accesses 2097395 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_avg_miss_latency 52065.516476 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency 40025.575526 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_hits 1786374 # number of ReadReq hits
|
|
system.l2c.ReadReq_miss_latency 16193469000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_rate 0.148289 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_misses 311021 # number of ReadReq misses
|
|
system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_miss_latency 12448754500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_rate 0.148289 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_misses 311020 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable_latency 810514000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.UpgradeReq_accesses 130249 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_avg_miss_latency 52272.455021 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency 40098.173498 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_miss_latency 6808434994 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_misses 130249 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency 5222747000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_misses 130249 # number of UpgradeReq MSHR misses
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_mshr_uncacheable_latency 1115855498 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.Writeback_accesses 430428 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_hits 430428 # number of Writeback hits
|
|
system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
|
system.l2c.avg_refs 4.596635 # Average number of references to valid blocks.
|
|
system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.demand_accesses 2397983 # number of demand (read+write) accesses
|
|
system.l2c.demand_avg_miss_latency 52211.235170 # average overall miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency 40117.751887 # average overall mshr miss latency
|
|
system.l2c.demand_hits 1786374 # number of demand (read+write) hits
|
|
system.l2c.demand_miss_latency 31932861331 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_rate 0.255051 # miss rate for demand accesses
|
|
system.l2c.demand_misses 611609 # number of demand (read+write) misses
|
|
system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_miss_latency 24536337996 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_rate 0.255051 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_misses 611608 # number of demand (read+write) MSHR misses
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.overall_accesses 2397983 # number of overall (read+write) accesses
|
|
system.l2c.overall_avg_miss_latency 52211.235170 # average overall miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency 40117.751887 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_hits 1786374 # number of overall hits
|
|
system.l2c.overall_miss_latency 31932861331 # number of overall miss cycles
|
|
system.l2c.overall_miss_rate 0.255051 # miss rate for overall accesses
|
|
system.l2c.overall_misses 611609 # number of overall misses
|
|
system.l2c.overall_mshr_hits 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_miss_latency 24536337996 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_rate 0.255051 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_misses 611608 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_uncacheable_latency 1926369498 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.l2c.replacements 396031 # number of replacements
|
|
system.l2c.sampled_refs 427707 # Sample count of references to valid blocks.
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.l2c.tagsinuse 30680.970322 # Cycle average of tags in use
|
|
system.l2c.total_refs 1966013 # Total number of references to valid blocks.
|
|
system.l2c.warmup_cycle 5645091000 # Cycle when the warmup percentage was hit.
|
|
system.l2c.writebacks 119091 # number of writebacks
|
|
system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
|
|
---------- End Simulation Statistics ----------
|