136 lines
4.7 KiB
C++
136 lines
4.7 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Stephen Hines
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*/
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#ifndef __ARCH_ARM_INSTS_BRANCH_HH__
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#define __ARCH_ARM_INSTS_BRANCH_HH__
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#include "arch/arm/insts/pred_inst.hh"
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namespace ArmISA
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{
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// Branch to a target computed with an immediate
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class BranchImm : public PredOp
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{
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protected:
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int32_t imm;
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public:
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BranchImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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int32_t _imm) :
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PredOp(mnem, _machInst, __opClass), imm(_imm)
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{}
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};
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// Conditionally Branch to a target computed with an immediate
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class BranchImmCond : public BranchImm
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{
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protected:
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// This will mask the condition code stored for PredOp. Ideally these two
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// class would cooperate, but they're not set up to do that at the moment.
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ConditionCode condCode;
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public:
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BranchImmCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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int32_t _imm, ConditionCode _condCode) :
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BranchImm(mnem, _machInst, __opClass, _imm), condCode(_condCode)
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{}
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};
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// Branch to a target computed with a register
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class BranchReg : public PredOp
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{
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protected:
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IntRegIndex op1;
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public:
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BranchReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _op1) :
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PredOp(mnem, _machInst, __opClass), op1(_op1)
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{}
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};
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// Conditionally Branch to a target computed with a register
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class BranchRegCond : public BranchReg
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{
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protected:
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// This will mask the condition code stored for PredOp. Ideally these two
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// class would cooperate, but they're not set up to do that at the moment.
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ConditionCode condCode;
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public:
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BranchRegCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _op1, ConditionCode _condCode) :
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BranchReg(mnem, _machInst, __opClass, _op1), condCode(_condCode)
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{}
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};
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// Branch to a target computed with two registers
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class BranchRegReg : public PredOp
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{
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protected:
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IntRegIndex op1;
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IntRegIndex op2;
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public:
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BranchRegReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _op1, IntRegIndex _op2) :
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PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2)
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{}
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};
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// Branch to a target computed with an immediate and a register
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class BranchImmReg : public PredOp
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{
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protected:
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int32_t imm;
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IntRegIndex op1;
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public:
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BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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int32_t _imm, IntRegIndex _op1) :
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PredOp(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
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{}
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};
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}
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#endif //__ARCH_ARM_INSTS_BRANCH_HH__
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