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Sascha Bischoff d7aef8be96 dev: Align BAR0 size to power of 2 for VirtIO devices 
When setting the size of a PCI BAR, the kernel only supports powers of
two (as per the PCI spec). Previously, the size was incorrectly read
by the kernel, and the address ranges assigned to the PCI devices
could overlap, resulting in gem5 crashes.  We now round up to the next
power of two.

Kudos to Sergei Trofimov who helped to debug this issue!

Change-Id: I54ca399b62ea07c09d4cd989b17dfa670e841bbe
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-by: Sergei Trofimov <sergei.trofimov@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2580
Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>
2017-04-03 16:36:15 +00:00
..
alpha style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
arm arm: correct register read bug in Pl390 GIC 2017-03-21 10:47:15 +00:00
i2c dev: Add missing SConscript in src/dev/i2c 2015-12-10 18:46:02 +00:00
mips style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
net dev: net/i8254xGBe add two more wakeup registers to ignore 2017-02-09 18:59:55 -05:00
pci style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
sparc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
storage dev: Revert 0a316996de76 [dev, sim: Added missing override...] 2016-08-16 10:59:15 +01:00
virtio dev: Align BAR0 size to power of 2 for VirtIO devices 2017-04-03 16:36:15 +00:00
x86 style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
baddev.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
baddev.hh AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
BadDevice.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
Device.py python: Fix incorrect header in the DmaDevice wrapper 2016-12-19 16:25:38 +00:00
dma_device.cc dev, kvm: Add a fast KVM-aware mode in DmaReadFifo 2017-03-07 11:14:28 +00:00
dma_device.hh dev, kvm: Add a fast KVM-aware mode in DmaReadFifo 2017-03-07 11:14:28 +00:00
intel_8254_timer.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
intel_8254_timer.hh sim: Refactor the serialization base class 2015-07-07 09:51:03 +01:00
io_device.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
io_device.hh sim: Decouple draining from the SimObject hierarchy 2015-07-07 09:51:05 +01:00
isa_fake.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
isa_fake.hh AddrRange: Transition from Range<T> to AddrRange 2012-09-19 06:15:44 -04:00
mc146818.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
mc146818.hh style: [patch 3/22] reduce include dependencies in some headers 2016-11-09 14:27:40 -06:00
pixelpump.cc dev: Add support for single-pass scan out in the PixelPump 2017-03-07 11:14:28 +00:00
pixelpump.hh dev: Add support for single-pass scan out in the PixelPump 2017-03-07 11:14:28 +00:00
platform.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
platform.hh dev: Rewrite PCI host functionality 2015-12-05 00:11:24 +00:00
Platform.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
ps2.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
ps2.hh style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
rtcreg.h dev: Clean up MC146818 register (A & B) handling 2013-06-03 12:28:41 +02:00
SConscript dev: Include DmaDevice in NULL builds 2016-12-19 16:25:38 +00:00
terminal.cc dev: Fix incorrect terminal backlog handling 2016-04-27 15:33:58 +01:00
terminal.hh base: Add support for changing output directories 2015-11-27 14:41:59 +00:00
Terminal.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
uart.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
uart.hh dev: Refactor terminal<->UART interface to make it more generic 2014-09-20 17:17:50 -04:00
Uart.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
uart8250.cc style: [patch 1/22] use /r/3648/ to reorganize includes 2016-11-09 14:27:37 -06:00
uart8250.hh misc: Add explicit overrides and fix other clang >= 3.5 issues 2015-10-12 04:08:01 -04:00