eddac53ff6
At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
280 lines
8.7 KiB
C++
280 lines
8.7 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#include "base/str.hh"
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#include "cpu/inorder/resources/resource_list.hh"
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#include "cpu/inorder/cpu.hh"
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#include "cpu/inorder/first_stage.hh"
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#include "cpu/inorder/resource_pool.hh"
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#include "debug/InOrderStage.hh"
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#include "params/InOrderTrace.hh"
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using namespace std;
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using namespace ThePipeline;
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FirstStage::FirstStage(Params *params, unsigned stage_num)
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: PipelineStage(params, stage_num), numFetchingThreads(1),
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fetchPolicy(FirstStage::RoundRobin)
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{
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for(ThreadID tid = 0; tid < this->numThreads; tid++) {
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stageStatus[tid] = Running;
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}
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}
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void
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FirstStage::setCPU(InOrderCPU *cpu_ptr)
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{
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cpu = cpu_ptr;
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fetchPriorityList = &cpu->fetchPriorityList;
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DPRINTF(InOrderStage, "Set CPU pointer.\n");
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}
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void
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FirstStage::squash(InstSeqNum squash_seq_num, ThreadID tid)
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{
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// Set status to squashing.
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//stageStatus[tid] = Squashing;
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// Clear the instruction list and skid buffer in case they have any
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// insts in them.
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DPRINTF(InOrderStage, "Removing instructions from stage instruction "
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"list.\n");
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while (!skidBuffer[tid].empty()) {
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if (skidBuffer[tid].front()->seqNum <= squash_seq_num) {
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DPRINTF(InOrderStage,"[tid:%i]: Cannot remove [sn:%i] because "
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"it's <= squashing seqNum %i.\n",
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tid,
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skidBuffer[tid].front()->seqNum,
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squash_seq_num);
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DPRINTF(InOrderStage, "[tid:%i]: Cannot remove incoming "
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"instructions before delay slot [sn:%i]. %i insts"
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"left.\n", tid, squash_seq_num,
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skidBuffer[tid].size());
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break;
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}
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DPRINTF(InOrderStage, "[tid:%i]: Removing instruction, [sn:%i] "
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"PC %s.\n", tid, skidBuffer[tid].front()->seqNum,
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skidBuffer[tid].front()->pc);
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skidBuffer[tid].pop_front();
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}
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// Now that squash has propagated to the first stage,
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// Alert CPU to remove instructions from the CPU instruction list.
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// @todo: Move this to the CPU object.
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cpu->removeInstsUntil(squash_seq_num, tid);
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}
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void
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FirstStage::squashDueToMemStall(InstSeqNum seq_num, ThreadID tid)
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{
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// Need to preserve the stalling instruction in first-stage
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// since the squash() from first stage also removes
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// the instruction from the CPU (removeInstsUntil). If that
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// functionality gets changed then you can move this offset.
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// (stalling instruction = seq_num + 1)
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squash(seq_num+1, tid);
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}
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void
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FirstStage::processStage(bool &status_change)
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{
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list<ThreadID>::iterator threads = activeThreads->begin();
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//Check stall and squash signals.
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while (threads != activeThreads->end()) {
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ThreadID tid = *threads++;
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status_change = checkSignalsAndUpdate(tid) || status_change;
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}
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while (instsProcessed < stageWidth) {
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ThreadID tid = getFetchingThread(fetchPolicy);
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if (tid >= 0) {
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DPRINTF(InOrderStage, "Processing [tid:%i]\n",tid);
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processThread(status_change, tid);
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DPRINTF(InOrderStage, "Done Processing [tid:%i]\n",tid);
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} else {
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DPRINTF(InOrderStage, "No more threads to fetch from.\n");
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break;
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}
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}
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if (instsProcessed > 0) {
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++runCycles;
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idle = false;
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} else {
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++idleCycles;
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idle = true;
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}
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}
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//@TODO: Note in documentation, that when you make a pipeline stage change,
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//then make sure you change the first stage too
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void
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FirstStage::processInsts(ThreadID tid)
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{
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bool all_reqs_completed = true;
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for (int insts_fetched = instsProcessed;
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insts_fetched < stageWidth;
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insts_fetched++) {
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DynInstPtr inst;
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bool new_inst = false;
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if (!skidBuffer[tid].empty()) {
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inst = skidBuffer[tid].front();
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} else {
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// Get new instruction.
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new_inst = true;
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inst = new InOrderDynInst(cpu,
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cpu->thread[tid],
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cpu->nextInstSeqNum(tid),
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tid,
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tid);
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#if TRACING_ON
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inst->traceData =
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tracer->getInstRecord(ThePipeline::NumStages,
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cpu->stageTracing,
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cpu->thread[tid]->getTC());
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#else
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inst->traceData = NULL;
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#endif // TRACING_ON
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// Add instruction to the CPU's list of instructions.
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inst->setInstListIt(cpu->addInst(inst));
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// Create Front-End Resource Schedule For Instruction
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inst->setFrontSked(cpu->frontEndSked);
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}
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int reqs_processed = 0;
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all_reqs_completed = processInstSchedule(inst, reqs_processed);
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// If the instruction isnt squashed & we've completed one request
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// Then we can officially count this instruction toward the stage's
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// bandwidth count
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if (reqs_processed > 0)
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instsProcessed++;
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if (!all_reqs_completed || !sendInstToNextStage(inst)) {
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if (new_inst) {
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DPRINTF(InOrderStage, "[tid:%u]: [sn:%u] Did not finish all "
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"requests for this stage. Keep in stage inst. "
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"list.\n", tid, inst->seqNum);
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skidBuffer[tid].push_back(inst);
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}
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block(tid);
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break;
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} else if (!skidBuffer[tid].empty()){
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DPRINTF(InOrderStage, "[tid:%u]: [sn:%u] Finished all "
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"requests for this stage.\n", tid, inst->seqNum);
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skidBuffer[tid].pop_front();
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}
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}
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// Record that stage has written to the time buffer for activity
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// tracking.
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if (instsProcessed) {
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wroteToTimeBuffer = true;
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}
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}
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ThreadID
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FirstStage::getFetchingThread(FetchPriority &fetch_priority)
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{
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ThreadID num_active_threads = cpu->numActiveThreads();
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if (num_active_threads > 1) {
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switch (fetch_priority) {
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case SingleThread:
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return cpu->activeThreadId();
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case RoundRobin:
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return roundRobin();
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default:
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return InvalidThreadID;
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}
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} else if (num_active_threads == 1) {
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ThreadID tid = *activeThreads->begin();
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if (stageStatus[tid] == Running ||
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stageStatus[tid] == Idle ||
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stageStatus[tid] == Unblocking) {
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return tid;
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} else {
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return InvalidThreadID;
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}
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} else {
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return InvalidThreadID;
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}
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}
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ThreadID
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FirstStage::roundRobin()
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{
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list<ThreadID>::iterator pri_iter = fetchPriorityList->begin();
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list<ThreadID>::iterator end = fetchPriorityList->end();
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ThreadID high_pri;
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while (pri_iter != end) {
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high_pri = *pri_iter;
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assert(high_pri <= numThreads);
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if (stageStatus[high_pri] == Running ||
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stageStatus[high_pri] == Idle ||
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stageStatus[high_pri] == Unblocking){
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fetchPriorityList->erase(pri_iter);
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fetchPriorityList->push_back(high_pri);
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return high_pri;
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}
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pri_iter++;
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}
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return InvalidThreadID;
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}
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