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gem5/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
Brad Beckmann 4eab18fd06 regess: protocol regression tester updates
2011-02-08 18:07:54 -08:00

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================ Begin RubySystem Configuration Print ================
RubySystem config:
random_seed: 1234
randomization: 0
cycle_period: 1
block_size_bytes: 64
block_size_bits: 6
memory_size_bytes: 134217728
memory_size_bits: 27
Network Configuration
---------------------
network: SIMPLE_NETWORK
topology:
virtual_net_0: active, ordered
virtual_net_1: active, ordered
virtual_net_2: active, unordered
virtual_net_3: active, unordered
virtual_net_4: active, unordered
virtual_net_5: active, unordered
virtual_net_6: inactive
virtual_net_7: inactive
virtual_net_8: inactive
virtual_net_9: inactive
Profiler Configuration
----------------------
periodic_stats_period: 1000000
================ End RubySystem Configuration Print ================
Real time: Feb/08/2011 17:57:03
Profiler Stats
--------------
Elapsed_time_in_seconds: 0
Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
Virtual_time_in_seconds: 0.34
Virtual_time_in_minutes: 0.00566667
Virtual_time_in_hours: 9.44444e-05
Virtual_time_in_days: 3.93519e-06
Ruby_current_time: 78448
Ruby_start_time: 0
Ruby_cycles: 78448
mbytes_resident: 35.3906
mbytes_total: 208.879
resident_ratio: 0.169469
ruby_cycles_executed: [ 78449 ]
Busy Controller Counts:
L1Cache-0:0
Directory-0:0
Busy Bank Count:0
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8154 | standard deviation: 52.8821 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5636 | standard deviation: 44.4401 | 0 0 2315 0 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.3952 | standard deviation: 74.7751 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.9728 | standard deviation: 63.5282 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average: 2 | standard deviation: 0 | 0 0 2784 ]
miss_latency_L2Cache: [binsize: 1 max: 13 count: 69 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 69 ]
miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.757 | standard deviation: 21.4255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 95 66 57 76 2 2 1 4 2 0 1 2 2 5 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_wCC_Times: 0
miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ]
imcomplete_dir_Times: 440
miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ]
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 13 count: 22 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 22 ]
miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.827 | standard deviation: 5.37952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 47 18 11 32 22 14 39 1 1 1 1 0 0 0 2 1 0 0 0 0 0 0 0 1 0 0 0 2 1 0 2 1 ]
miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ]
miss_latency_LD_L2Cache: [binsize: 1 max: 13 count: 36 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 36 ]
miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 156.747 | standard deviation: 24.5989 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 35 24 16 16 26 0 1 1 0 1 0 0 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average: 2 | standard deviation: 0 | 0 0 236 ]
miss_latency_ST_L2Cache: [binsize: 1 max: 13 count: 11 average: 13 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 11 ]
miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 168.149 | standard deviation: 46.0633 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 7 6 7 5 10 0 0 0 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Request vs. RubySystem State Profile
--------------------------------
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Message Delayed Cycles
----------------------
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
user_time: 0
system_time: 0
page_reclaims: 10290
page_faults: 0
swaps: 0
block_inputs: 0
block_outputs: 0
Network Stats
-------------
total_msg_count_Request_Control: 1323 10584
total_msg_count_Response_Data: 1323 95256
total_msg_count_Writeback_Data: 243 17496
total_msg_count_Writeback_Control: 3582 28656
total_msg_count_Unblock_Control: 1320 10560
total_msgs: 7791 total_bytes: 162552
switch_0_inlinks: 2
switch_0_outlinks: 2
links_utilized_percent_switch_0: 0.110822
links_utilized_percent_switch_0_link_0: 0.0700145 bw: 640000 base_latency: 1
links_utilized_percent_switch_0_link_1: 0.151629 bw: 160000 base_latency: 1
outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_0_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
links_utilized_percent_switch_1: 0.158983
links_utilized_percent_switch_1_link_0: 0.0379073 bw: 640000 base_latency: 1
links_utilized_percent_switch_1_link_1: 0.280058 bw: 160000 base_latency: 1
outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_0_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_1_link_1_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
links_utilized_percent_switch_2: 0.215844
links_utilized_percent_switch_2_link_0: 0.280058 bw: 160000 base_latency: 1
links_utilized_percent_switch_2_link_1: 0.151629 bw: 160000 base_latency: 1
outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1
outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1
Cache Stats: system.ruby.cpu_ruby_ports.icache
system.ruby.cpu_ruby_ports.icache_total_misses: 270
system.ruby.cpu_ruby_ports.icache_total_demand_misses: 270
system.ruby.cpu_ruby_ports.icache_total_prefetches: 0
system.ruby.cpu_ruby_ports.icache_total_sw_prefetches: 0
system.ruby.cpu_ruby_ports.icache_total_hw_prefetches: 0
system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100%
system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode: 270 100%
Cache Stats: system.ruby.cpu_ruby_ports.dcache
system.ruby.cpu_ruby_ports.dcache_total_misses: 240
system.ruby.cpu_ruby_ports.dcache_total_demand_misses: 240
system.ruby.cpu_ruby_ports.dcache_total_prefetches: 0
system.ruby.cpu_ruby_ports.dcache_total_sw_prefetches: 0
system.ruby.cpu_ruby_ports.dcache_total_hw_prefetches: 0
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 75.8333%
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 24.1667%
system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 240 100%
Cache Stats: system.l1_cntrl0.L2cacheMemory
system.l1_cntrl0.L2cacheMemory_total_misses: 510
system.l1_cntrl0.L2cacheMemory_total_demand_misses: 510
system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
system.l1_cntrl0.L2cacheMemory_request_type_LD: 35.6863%
system.l1_cntrl0.L2cacheMemory_request_type_ST: 11.3725%
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 52.9412%
system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 510 100%
--- L1Cache ---
- Event Counts -
Load [422 ] 422
Ifetch [2591 ] 2591
Store [298 ] 298
L2_Replacement [425 ] 425
L1_to_L2 [502 ] 502
Trigger_L2_to_L1D [47 ] 47
Trigger_L2_to_L1I [22 ] 22
Complete_L2_to_L1 [69 ] 69
Other_GETX [0 ] 0
Other_GETS [0 ] 0
Merged_GETS [0 ] 0
Other_GETS_No_Mig [0 ] 0
NC_DMA_GETS [0 ] 0
Invalidate [0 ] 0
Ack [0 ] 0
Shared_Ack [0 ] 0
Data [0 ] 0
Shared_Data [0 ] 0
Exclusive_Data [441 ] 441
Writeback_Ack [425 ] 425
Writeback_Nack [0 ] 0
All_acks [0 ] 0
All_acks_no_sharers [441 ] 441
- Transitions -
I Load [146 ] 146
I Ifetch [248 ] 248
I Store [47 ] 47
I L2_Replacement [0 ] 0
I L1_to_L2 [0 ] 0
I Trigger_L2_to_L1D [0 ] 0
I Trigger_L2_to_L1I [0 ] 0
I Other_GETX [0 ] 0
I Other_GETS [0 ] 0
I Other_GETS_No_Mig [0 ] 0
I NC_DMA_GETS [0 ] 0
I Invalidate [0 ] 0
S Load [0 ] 0
S Ifetch [0 ] 0
S Store [0 ] 0
S L2_Replacement [0 ] 0
S L1_to_L2 [0 ] 0
S Trigger_L2_to_L1D [0 ] 0
S Trigger_L2_to_L1I [0 ] 0
S Other_GETX [0 ] 0
S Other_GETS [0 ] 0
S Other_GETS_No_Mig [0 ] 0
S NC_DMA_GETS [0 ] 0
S Invalidate [0 ] 0
O Load [0 ] 0
O Ifetch [0 ] 0
O Store [0 ] 0
O L2_Replacement [0 ] 0
O L1_to_L2 [0 ] 0
O Trigger_L2_to_L1D [0 ] 0
O Trigger_L2_to_L1I [0 ] 0
O Other_GETX [0 ] 0
O Other_GETS [0 ] 0
O Merged_GETS [0 ] 0
O Other_GETS_No_Mig [0 ] 0
O NC_DMA_GETS [0 ] 0
O Invalidate [0 ] 0
M Load [131 ] 131
M Ifetch [2337 ] 2337
M Store [36 ] 36
M L2_Replacement [344 ] 344
M L1_to_L2 [397 ] 397
M Trigger_L2_to_L1D [23 ] 23
M Trigger_L2_to_L1I [22 ] 22
M Other_GETX [0 ] 0
M Other_GETS [0 ] 0
M Merged_GETS [0 ] 0
M Other_GETS_No_Mig [0 ] 0
M NC_DMA_GETS [0 ] 0
M Invalidate [0 ] 0
MM Load [138 ] 138
MM Ifetch [0 ] 0
MM Store [211 ] 211
MM L2_Replacement [81 ] 81
MM L1_to_L2 [105 ] 105
MM Trigger_L2_to_L1D [24 ] 24
MM Trigger_L2_to_L1I [0 ] 0
MM Other_GETX [0 ] 0
MM Other_GETS [0 ] 0
MM Merged_GETS [0 ] 0
MM Other_GETS_No_Mig [0 ] 0
MM NC_DMA_GETS [0 ] 0
MM Invalidate [0 ] 0
IM Load [0 ] 0
IM Ifetch [0 ] 0
IM Store [0 ] 0
IM L2_Replacement [0 ] 0
IM L1_to_L2 [0 ] 0
IM Other_GETX [0 ] 0
IM Other_GETS [0 ] 0
IM Other_GETS_No_Mig [0 ] 0
IM NC_DMA_GETS [0 ] 0
IM Invalidate [0 ] 0
IM Ack [0 ] 0
IM Data [0 ] 0
IM Exclusive_Data [47 ] 47
SM Load [0 ] 0
SM Ifetch [0 ] 0
SM Store [0 ] 0
SM L2_Replacement [0 ] 0
SM L1_to_L2 [0 ] 0
SM Other_GETX [0 ] 0
SM Other_GETS [0 ] 0
SM Other_GETS_No_Mig [0 ] 0
SM NC_DMA_GETS [0 ] 0
SM Invalidate [0 ] 0
SM Ack [0 ] 0
SM Data [0 ] 0
SM Exclusive_Data [0 ] 0
OM Load [0 ] 0
OM Ifetch [0 ] 0
OM Store [0 ] 0
OM L2_Replacement [0 ] 0
OM L1_to_L2 [0 ] 0
OM Other_GETX [0 ] 0
OM Other_GETS [0 ] 0
OM Merged_GETS [0 ] 0
OM Other_GETS_No_Mig [0 ] 0
OM NC_DMA_GETS [0 ] 0
OM Invalidate [0 ] 0
OM Ack [0 ] 0
OM All_acks [0 ] 0
OM All_acks_no_sharers [0 ] 0
ISM Load [0 ] 0
ISM Ifetch [0 ] 0
ISM Store [0 ] 0
ISM L2_Replacement [0 ] 0
ISM L1_to_L2 [0 ] 0
ISM Ack [0 ] 0
ISM All_acks_no_sharers [0 ] 0
M_W Load [0 ] 0
M_W Ifetch [0 ] 0
M_W Store [0 ] 0
M_W L2_Replacement [0 ] 0
M_W L1_to_L2 [0 ] 0
M_W Ack [0 ] 0
M_W All_acks_no_sharers [394 ] 394
MM_W Load [0 ] 0
MM_W Ifetch [0 ] 0
MM_W Store [0 ] 0
MM_W L2_Replacement [0 ] 0
MM_W L1_to_L2 [0 ] 0
MM_W Ack [0 ] 0
MM_W All_acks_no_sharers [47 ] 47
IS Load [0 ] 0
IS Ifetch [0 ] 0
IS Store [0 ] 0
IS L2_Replacement [0 ] 0
IS L1_to_L2 [0 ] 0
IS Other_GETX [0 ] 0
IS Other_GETS [0 ] 0
IS Other_GETS_No_Mig [0 ] 0
IS NC_DMA_GETS [0 ] 0
IS Invalidate [0 ] 0
IS Ack [0 ] 0
IS Shared_Ack [0 ] 0
IS Data [0 ] 0
IS Shared_Data [0 ] 0
IS Exclusive_Data [394 ] 394
SS Load [0 ] 0
SS Ifetch [0 ] 0
SS Store [0 ] 0
SS L2_Replacement [0 ] 0
SS L1_to_L2 [0 ] 0
SS Ack [0 ] 0
SS Shared_Ack [0 ] 0
SS All_acks [0 ] 0
SS All_acks_no_sharers [0 ] 0
OI Load [0 ] 0
OI Ifetch [0 ] 0
OI Store [0 ] 0
OI L2_Replacement [0 ] 0
OI L1_to_L2 [0 ] 0
OI Other_GETX [0 ] 0
OI Other_GETS [0 ] 0
OI Merged_GETS [0 ] 0
OI Other_GETS_No_Mig [0 ] 0
OI NC_DMA_GETS [0 ] 0
OI Invalidate [0 ] 0
OI Writeback_Ack [0 ] 0
MI Load [7 ] 7
MI Ifetch [6 ] 6
MI Store [4 ] 4
MI L2_Replacement [0 ] 0
MI L1_to_L2 [0 ] 0
MI Other_GETX [0 ] 0
MI Other_GETS [0 ] 0
MI Merged_GETS [0 ] 0
MI Other_GETS_No_Mig [0 ] 0
MI NC_DMA_GETS [0 ] 0
MI Invalidate [0 ] 0
MI Writeback_Ack [425 ] 425
II Load [0 ] 0
II Ifetch [0 ] 0
II Store [0 ] 0
II L2_Replacement [0 ] 0
II L1_to_L2 [0 ] 0
II Other_GETX [0 ] 0
II Other_GETS [0 ] 0
II Other_GETS_No_Mig [0 ] 0
II NC_DMA_GETS [0 ] 0
II Invalidate [0 ] 0
II Writeback_Ack [0 ] 0
II Writeback_Nack [0 ] 0
IT Load [0 ] 0
IT Ifetch [0 ] 0
IT Store [0 ] 0
IT L2_Replacement [0 ] 0
IT L1_to_L2 [0 ] 0
IT Complete_L2_to_L1 [0 ] 0
IT Other_GETX [0 ] 0
IT Other_GETS [0 ] 0
IT Merged_GETS [0 ] 0
IT Other_GETS_No_Mig [0 ] 0
IT NC_DMA_GETS [0 ] 0
IT Invalidate [0 ] 0
ST Load [0 ] 0
ST Ifetch [0 ] 0
ST Store [0 ] 0
ST L2_Replacement [0 ] 0
ST L1_to_L2 [0 ] 0
ST Complete_L2_to_L1 [0 ] 0
ST Other_GETX [0 ] 0
ST Other_GETS [0 ] 0
ST Merged_GETS [0 ] 0
ST Other_GETS_No_Mig [0 ] 0
ST NC_DMA_GETS [0 ] 0
ST Invalidate [0 ] 0
OT Load [0 ] 0
OT Ifetch [0 ] 0
OT Store [0 ] 0
OT L2_Replacement [0 ] 0
OT L1_to_L2 [0 ] 0
OT Complete_L2_to_L1 [0 ] 0
OT Other_GETX [0 ] 0
OT Other_GETS [0 ] 0
OT Merged_GETS [0 ] 0
OT Other_GETS_No_Mig [0 ] 0
OT NC_DMA_GETS [0 ] 0
OT Invalidate [0 ] 0
MT Load [0 ] 0
MT Ifetch [0 ] 0
MT Store [0 ] 0
MT L2_Replacement [0 ] 0
MT L1_to_L2 [0 ] 0
MT Complete_L2_to_L1 [45 ] 45
MT Other_GETX [0 ] 0
MT Other_GETS [0 ] 0
MT Merged_GETS [0 ] 0
MT Other_GETS_No_Mig [0 ] 0
MT NC_DMA_GETS [0 ] 0
MT Invalidate [0 ] 0
MMT Load [0 ] 0
MMT Ifetch [0 ] 0
MMT Store [0 ] 0
MMT L2_Replacement [0 ] 0
MMT L1_to_L2 [0 ] 0
MMT Complete_L2_to_L1 [24 ] 24
MMT Other_GETX [0 ] 0
MMT Other_GETS [0 ] 0
MMT Merged_GETS [0 ] 0
MMT Other_GETS_No_Mig [0 ] 0
MMT NC_DMA_GETS [0 ] 0
MMT Invalidate [0 ] 0
Cache Stats: system.dir_cntrl0.probeFilter
system.dir_cntrl0.probeFilter_total_misses: 0
system.dir_cntrl0.probeFilter_total_demand_misses: 0
system.dir_cntrl0.probeFilter_total_prefetches: 0
system.dir_cntrl0.probeFilter_total_sw_prefetches: 0
system.dir_cntrl0.probeFilter_total_hw_prefetches: 0
Memory controller: system.dir_cntrl0.memBuffer:
memory_total_requests: 522
memory_reads: 441
memory_writes: 81
memory_refreshes: 164
memory_total_request_delays: 151
memory_delays_per_request: 0.289272
memory_delays_in_input_queue: 2
memory_delays_behind_head_of_bank_queue: 0
memory_delays_stalled_at_head_of_bank_queue: 149
memory_stalls_for_bank_busy: 22
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
memory_stalls_for_arbitration: 7
memory_stalls_for_bus: 26
memory_stalls_for_tfaw: 0
memory_stalls_for_read_write_turnaround: 94
memory_stalls_for_read_read_turnaround: 0
accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62
--- Directory ---
- Event Counts -
GETX [53 ] 53
GETS [410 ] 410
PUT [425 ] 425
Unblock [0 ] 0
UnblockS [0 ] 0
UnblockM [440 ] 440
Writeback_Clean [0 ] 0
Writeback_Dirty [0 ] 0
Writeback_Exclusive_Clean [344 ] 344
Writeback_Exclusive_Dirty [81 ] 81
Pf_Replacement [0 ] 0
DMA_READ [0 ] 0
DMA_WRITE [0 ] 0
Memory_Data [441 ] 441
Memory_Ack [81 ] 81
Ack [0 ] 0
Shared_Ack [0 ] 0
Shared_Data [0 ] 0
Data [0 ] 0
Exclusive_Data [0 ] 0
All_acks_and_shared_data [0 ] 0
All_acks_and_owner_data [0 ] 0
All_acks_and_data_no_sharers [0 ] 0
All_Unblocks [0 ] 0
- Transitions -
NX GETX [0 ] 0
NX GETS [0 ] 0
NX PUT [0 ] 0
NX Pf_Replacement [0 ] 0
NX DMA_READ [0 ] 0
NX DMA_WRITE [0 ] 0
NO GETX [0 ] 0
NO GETS [0 ] 0
NO PUT [425 ] 425
NO Pf_Replacement [0 ] 0
NO DMA_READ [0 ] 0
NO DMA_WRITE [0 ] 0
S GETX [0 ] 0
S GETS [0 ] 0
S PUT [0 ] 0
S Pf_Replacement [0 ] 0
S DMA_READ [0 ] 0
S DMA_WRITE [0 ] 0
O GETX [0 ] 0
O GETS [0 ] 0
O PUT [0 ] 0
O Pf_Replacement [0 ] 0
O DMA_READ [0 ] 0
O DMA_WRITE [0 ] 0
E GETX [47 ] 47
E GETS [394 ] 394
E PUT [0 ] 0
E DMA_READ [0 ] 0
E DMA_WRITE [0 ] 0
O_R GETX [0 ] 0
O_R GETS [0 ] 0
O_R PUT [0 ] 0
O_R Pf_Replacement [0 ] 0
O_R DMA_READ [0 ] 0
O_R DMA_WRITE [0 ] 0
O_R Ack [0 ] 0
O_R All_acks_and_data_no_sharers [0 ] 0
S_R GETX [0 ] 0
S_R GETS [0 ] 0
S_R PUT [0 ] 0
S_R Pf_Replacement [0 ] 0
S_R DMA_READ [0 ] 0
S_R DMA_WRITE [0 ] 0
S_R Ack [0 ] 0
S_R Data [0 ] 0
S_R All_acks_and_data_no_sharers [0 ] 0
NO_R GETX [0 ] 0
NO_R GETS [0 ] 0
NO_R PUT [0 ] 0
NO_R Pf_Replacement [0 ] 0
NO_R DMA_READ [0 ] 0
NO_R DMA_WRITE [0 ] 0
NO_R Ack [0 ] 0
NO_R Data [0 ] 0
NO_R Exclusive_Data [0 ] 0
NO_R All_acks_and_data_no_sharers [0 ] 0
NO_B GETX [0 ] 0
NO_B GETS [0 ] 0
NO_B PUT [0 ] 0
NO_B UnblockS [0 ] 0
NO_B UnblockM [440 ] 440
NO_B Pf_Replacement [0 ] 0
NO_B DMA_READ [0 ] 0
NO_B DMA_WRITE [0 ] 0
NO_B_X GETX [0 ] 0
NO_B_X GETS [0 ] 0
NO_B_X PUT [0 ] 0
NO_B_X UnblockS [0 ] 0
NO_B_X UnblockM [0 ] 0
NO_B_X Pf_Replacement [0 ] 0
NO_B_X DMA_READ [0 ] 0
NO_B_X DMA_WRITE [0 ] 0
NO_B_S GETX [0 ] 0
NO_B_S GETS [0 ] 0
NO_B_S PUT [0 ] 0
NO_B_S UnblockS [0 ] 0
NO_B_S UnblockM [0 ] 0
NO_B_S Pf_Replacement [0 ] 0
NO_B_S DMA_READ [0 ] 0
NO_B_S DMA_WRITE [0 ] 0
NO_B_S_W GETX [0 ] 0
NO_B_S_W GETS [0 ] 0
NO_B_S_W PUT [0 ] 0
NO_B_S_W UnblockS [0 ] 0
NO_B_S_W Pf_Replacement [0 ] 0
NO_B_S_W DMA_READ [0 ] 0
NO_B_S_W DMA_WRITE [0 ] 0
NO_B_S_W All_Unblocks [0 ] 0
O_B GETX [0 ] 0
O_B GETS [0 ] 0
O_B PUT [0 ] 0
O_B UnblockS [0 ] 0
O_B UnblockM [0 ] 0
O_B Pf_Replacement [0 ] 0
O_B DMA_READ [0 ] 0
O_B DMA_WRITE [0 ] 0
NO_B_W GETX [0 ] 0
NO_B_W GETS [0 ] 0
NO_B_W PUT [0 ] 0
NO_B_W UnblockS [0 ] 0
NO_B_W UnblockM [0 ] 0
NO_B_W Pf_Replacement [0 ] 0
NO_B_W DMA_READ [0 ] 0
NO_B_W DMA_WRITE [0 ] 0
NO_B_W Memory_Data [441 ] 441
O_B_W GETX [0 ] 0
O_B_W GETS [0 ] 0
O_B_W PUT [0 ] 0
O_B_W UnblockS [0 ] 0
O_B_W Pf_Replacement [0 ] 0
O_B_W DMA_READ [0 ] 0
O_B_W DMA_WRITE [0 ] 0
O_B_W Memory_Data [0 ] 0
NO_W GETX [0 ] 0
NO_W GETS [0 ] 0
NO_W PUT [0 ] 0
NO_W Pf_Replacement [0 ] 0
NO_W DMA_READ [0 ] 0
NO_W DMA_WRITE [0 ] 0
NO_W Memory_Data [0 ] 0
O_W GETX [0 ] 0
O_W GETS [0 ] 0
O_W PUT [0 ] 0
O_W Pf_Replacement [0 ] 0
O_W DMA_READ [0 ] 0
O_W DMA_WRITE [0 ] 0
O_W Memory_Data [0 ] 0
NO_DW_B_W GETX [0 ] 0
NO_DW_B_W GETS [0 ] 0
NO_DW_B_W PUT [0 ] 0
NO_DW_B_W Pf_Replacement [0 ] 0
NO_DW_B_W DMA_READ [0 ] 0
NO_DW_B_W DMA_WRITE [0 ] 0
NO_DW_B_W Ack [0 ] 0
NO_DW_B_W Data [0 ] 0
NO_DW_B_W Exclusive_Data [0 ] 0
NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0
NO_DR_B_W GETX [0 ] 0
NO_DR_B_W GETS [0 ] 0
NO_DR_B_W PUT [0 ] 0
NO_DR_B_W Pf_Replacement [0 ] 0
NO_DR_B_W DMA_READ [0 ] 0
NO_DR_B_W DMA_WRITE [0 ] 0
NO_DR_B_W Memory_Data [0 ] 0
NO_DR_B_W Ack [0 ] 0
NO_DR_B_W Shared_Ack [0 ] 0
NO_DR_B_W Shared_Data [0 ] 0
NO_DR_B_W Data [0 ] 0
NO_DR_B_W Exclusive_Data [0 ] 0
NO_DR_B_D GETX [0 ] 0
NO_DR_B_D GETS [0 ] 0
NO_DR_B_D PUT [0 ] 0
NO_DR_B_D Pf_Replacement [0 ] 0
NO_DR_B_D DMA_READ [0 ] 0
NO_DR_B_D DMA_WRITE [0 ] 0
NO_DR_B_D Ack [0 ] 0
NO_DR_B_D Shared_Ack [0 ] 0
NO_DR_B_D Shared_Data [0 ] 0
NO_DR_B_D Data [0 ] 0
NO_DR_B_D Exclusive_Data [0 ] 0
NO_DR_B_D All_acks_and_shared_data [0 ] 0
NO_DR_B_D All_acks_and_owner_data [0 ] 0
NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0
NO_DR_B GETX [0 ] 0
NO_DR_B GETS [0 ] 0
NO_DR_B PUT [0 ] 0
NO_DR_B Pf_Replacement [0 ] 0
NO_DR_B DMA_READ [0 ] 0
NO_DR_B DMA_WRITE [0 ] 0
NO_DR_B Ack [0 ] 0
NO_DR_B Shared_Ack [0 ] 0
NO_DR_B Shared_Data [0 ] 0
NO_DR_B Data [0 ] 0
NO_DR_B Exclusive_Data [0 ] 0
NO_DR_B All_acks_and_shared_data [0 ] 0
NO_DR_B All_acks_and_owner_data [0 ] 0
NO_DR_B All_acks_and_data_no_sharers [0 ] 0
NO_DW_W GETX [0 ] 0
NO_DW_W GETS [0 ] 0
NO_DW_W PUT [0 ] 0
NO_DW_W Pf_Replacement [0 ] 0
NO_DW_W DMA_READ [0 ] 0
NO_DW_W DMA_WRITE [0 ] 0
NO_DW_W Memory_Ack [0 ] 0
O_DR_B_W GETX [0 ] 0
O_DR_B_W GETS [0 ] 0
O_DR_B_W PUT [0 ] 0
O_DR_B_W Pf_Replacement [0 ] 0
O_DR_B_W DMA_READ [0 ] 0
O_DR_B_W DMA_WRITE [0 ] 0
O_DR_B_W Memory_Data [0 ] 0
O_DR_B_W Ack [0 ] 0
O_DR_B_W Shared_Ack [0 ] 0
O_DR_B GETX [0 ] 0
O_DR_B GETS [0 ] 0
O_DR_B PUT [0 ] 0
O_DR_B Pf_Replacement [0 ] 0
O_DR_B DMA_READ [0 ] 0
O_DR_B DMA_WRITE [0 ] 0
O_DR_B Ack [0 ] 0
O_DR_B Shared_Ack [0 ] 0
O_DR_B All_acks_and_owner_data [0 ] 0
O_DR_B All_acks_and_data_no_sharers [0 ] 0
WB GETX [4 ] 4
WB GETS [14 ] 14
WB PUT [0 ] 0
WB Unblock [0 ] 0
WB Writeback_Clean [0 ] 0
WB Writeback_Dirty [0 ] 0
WB Writeback_Exclusive_Clean [344 ] 344
WB Writeback_Exclusive_Dirty [81 ] 81
WB Pf_Replacement [0 ] 0
WB DMA_READ [0 ] 0
WB DMA_WRITE [0 ] 0
WB_O_W GETX [0 ] 0
WB_O_W GETS [0 ] 0
WB_O_W PUT [0 ] 0
WB_O_W Pf_Replacement [0 ] 0
WB_O_W DMA_READ [0 ] 0
WB_O_W DMA_WRITE [0 ] 0
WB_O_W Memory_Ack [0 ] 0
WB_E_W GETX [2 ] 2
WB_E_W GETS [2 ] 2
WB_E_W PUT [0 ] 0
WB_E_W Pf_Replacement [0 ] 0
WB_E_W DMA_READ [0 ] 0
WB_E_W DMA_WRITE [0 ] 0
WB_E_W Memory_Ack
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