sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity
gem5/src/gpu-compute
History
Brandon Potter d3d983caf9 syscall_emul: [patch 10/22] refactor fdentry and add fdarray class 
Several large changes happen in this patch.

The FDEntry class is rewritten so that file descriptors now correspond to
types: 'File' which is normal file-backed file with the file open on the
host machine, 'Pipe' which is a pipe that has been opened on the host machine,
and 'Device' which does not have an open file on the host yet acts as a pseudo
device with which to issue ioctls. Other types which might be added in the
future are directory entries and sockets (off the top of my head).

The FDArray class was create to hold most of the file descriptor handling
that was stuffed into the Process class. It uses shared pointers and
the std::array type to hold the FDEntries mentioned above.

The changes to these two classes needed to be propagated out to the rest
of the code so there were quite a few changes for that. Also, comments were
added where I thought they were needed to help others and extend our
DOxygen coverage.
2016-11-09 14:27:42 -06:00
..
brig_object.cc hsail: remove the panic guarding function directives 2016-12-02 18:01:42 -05:00
brig_object.hh gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
cl_driver.cc syscall_emul: [patch 10/22] refactor fdentry and add fdarray class 2016-11-09 14:27:42 -06:00
cl_driver.hh syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead 2016-11-09 14:27:40 -06:00
cl_event.hh gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
compute_unit.cc gpu-compute: support in-order data delivery in GM pipe 2016-10-26 22:48:28 -04:00
compute_unit.hh gpu-compute: use System cache line size in the GPU 2016-10-26 22:47:47 -04:00
condition_register_state.cc gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex() 2016-10-26 22:47:49 -04:00
condition_register_state.hh gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex() 2016-10-26 22:47:49 -04:00
dispatcher.cc gpu-compute: fix typo in GPUDispatcher 2016-09-16 14:47:19 -04:00
dispatcher.hh gpu-compute: Adding ioctl for HW context size 2016-09-16 12:27:56 -04:00
exec_stage.cc gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
exec_stage.hh gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
fetch_stage.cc gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
fetch_stage.hh gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
fetch_unit.cc gpu-compute: use System cache line size in the GPU 2016-10-26 22:47:47 -04:00
fetch_unit.hh gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
global_memory_pipeline.cc gpu-compute: support in-order data delivery in GM pipe 2016-10-26 22:48:28 -04:00
global_memory_pipeline.hh gpu-compute: support in-order data delivery in GM pipe 2016-10-26 22:48:28 -04:00
GPU.py gpu-compute: support in-order data delivery in GM pipe 2016-10-26 22:48:28 -04:00
gpu_dyn_inst.cc gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex() 2016-10-26 22:47:49 -04:00
gpu_dyn_inst.hh gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex() 2016-10-26 22:47:49 -04:00
gpu_exec_context.cc gpu-compute: fix segfault when constructing GPUExecContext 2016-11-21 15:40:03 -05:00
gpu_exec_context.hh gpu-compute: fix segfault when constructing GPUExecContext 2016-11-21 15:40:03 -05:00
gpu_static_inst.cc gpu-compute, hsail: make the PC a byte address, not an instruction index 2016-10-26 22:47:43 -04:00
gpu_static_inst.hh hsail,gpu-compute: fixes to appease clang++ 2016-10-26 22:48:45 -04:00
gpu_tlb.cc hsail,gpu-compute: fixes to appease clang++ 2016-10-26 22:48:45 -04:00
gpu_tlb.hh gpu-compute: init valid field of GpuTlbEntry in default ctor 2016-11-21 15:38:30 -05:00
GPUStaticInstFlags.py gpu-compute: remove inst enums and use bit flag for attributes 2016-10-26 22:47:11 -04:00
hsa_code.hh gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
hsa_kernel_info.hh gpu-compute: Adding ioctl for HW context size 2016-09-16 12:27:56 -04:00
hsa_object.cc gpu-compute: remove brig_object.hh from hsa_object.cc 2016-02-17 11:46:02 -05:00
hsa_object.hh gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
hsail_code.cc gpu-compute, hsail: make the PC a byte address, not an instruction index 2016-10-26 22:47:43 -04:00
hsail_code.hh gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
kernel_cfg.cc gpu-compute, hsail: make the PC a byte address, not an instruction index 2016-10-26 22:47:43 -04:00
kernel_cfg.hh gpu-compute, hsail: make the PC a byte address, not an instruction index 2016-10-26 22:47:43 -04:00
lds_state.cc gpu-compute: remove inst enums and use bit flag for attributes 2016-10-26 22:47:11 -04:00
lds_state.hh gpu-compute: remove inst enums and use bit flag for attributes 2016-10-26 22:47:11 -04:00
LdsState.py gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
local_memory_pipeline.cc hsail, gpu-compute: remove doGm/SmReturn add completeAcc 2016-10-26 22:47:19 -04:00
local_memory_pipeline.hh hsail, gpu-compute: remove doGm/SmReturn add completeAcc 2016-10-26 22:47:19 -04:00
misc.hh gpu-compute: parametrize Wavefront size 2016-06-09 11:24:55 -04:00
ndrange.hh mem: Remove threadId from memory request class 2016-04-07 09:30:20 -05:00
of_scheduling_policy.cc gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
of_scheduling_policy.hh gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
pool_manager.cc gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
pool_manager.hh gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
qstruct.hh gpu-compute: Remove WFContext 2016-09-16 12:26:03 -04:00
rr_scheduling_policy.cc gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
rr_scheduling_policy.hh gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
schedule_stage.cc gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
schedule_stage.hh gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
scheduler.cc gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
scheduler.hh gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
scheduling_policy.hh gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
SConscript gpu-compute: remove inst enums and use bit flag for attributes 2016-10-26 22:47:11 -04:00
scoreboard_check_stage.cc gpu-compute: remove unused variable from scoreboard check stage 2016-03-21 11:26:23 -04:00
scoreboard_check_stage.hh gpu-compute: remove unused variable from scoreboard check stage 2016-03-21 11:26:23 -04:00
shader.cc gpu-compute: use System cache line size in the GPU 2016-10-26 22:47:47 -04:00
shader.hh gpu-compute: remove inst enums and use bit flag for attributes 2016-10-26 22:47:11 -04:00
simple_pool_manager.cc gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
simple_pool_manager.hh gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
tlb_coalescer.cc stats: Fixing regStats function for some SimObjects 2016-06-06 17:16:43 +01:00
tlb_coalescer.hh gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00
vector_register_file.cc gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex() 2016-10-26 22:47:49 -04:00
vector_register_file.hh style: [patch 3/22] reduce include dependencies in some headers 2016-11-09 14:27:40 -06:00
vector_register_state.cc gpu-compute: parametrize Wavefront size 2016-06-09 11:24:55 -04:00
vector_register_state.hh gpu-compute: parametrize Wavefront size 2016-06-09 11:24:55 -04:00
wavefront.cc gpu-compute: add gpu_isa.hh to switch hdrs, add GPUISA to WF 2016-10-26 22:47:38 -04:00
wavefront.hh gpu-compute: add gpu_isa.hh to switch hdrs, add GPUISA to WF 2016-10-26 22:47:38 -04:00
X86GPUTLB.py gpu-compute: AMD's baseline GPU model 2016-01-19 14:28:22 -05:00